This paper presents the characterisation and testing of the first wafer-scale monolithic stitched sensor (MOSS) prototype developed for the ALICE ITS3 upgrade that is to be installed during the LHC Long Shutdown 3 (2026-2030). The MOSS chip design is driven by the truly cylindrical detector geometry that imposes that each layer is built out of two wafer-sized, bent silicon chips. The stitching technique is employed to fabricate sensors with dimensions of 1.4 cm x 25.9 cm, thinned to 50 mu m. The chip architecture, the in-pixel front-end, the laboratory and in-beam characterisation, the susceptibility to single-event effects, and the series testing are discussed. The testing campaign validates the design of a wafer-scale stitched sensor and the performance of the pixel matrix to be within the ITS3 requirements. The MOSS chip demonstrates the feasibility of the ITS3 detector concept and provides insights for further optimisation and development.

For the Inner Tracking System 3 (ITS3) upgrade, the ALICE experiment at CERN requires monolithic active pixel sensors of dimensions up to 97 mm×266 mm, occupying a large fraction of a 300 mm wafer. To manufacture such a wafer-scale device, larger than the single design reticle size, stitching is employed. The MOnolithic Stitched Sensor (MOSS) is a prototype silicon pixel sensor of 14 mm×259 mm size with the primary goal of understanding the stitching technique and yield. Given the large size, high yield is paramount for the ITS3 sensors, and an in-depth yield characterization was performed on these MOSS sensors. In a collaborative effort, the foundry adapted the metal stack to the requirements of the project, but recurrent fault signatures were discovered with various frequencies across all 20 wafers tested, and correlated through dedicated measurements and analyses. Following these findings, the foundry implemented a mitigation strategy to avoid the issue in the future. This article does not describe process details but concentrates on the measurements and analysis method.

Within the context of the ALICE ITS3 collaboration, a set of MAPS small-scale test structures were developed using the 65 nm TPSCo CMOS imaging process with the upgrade of the ALICE inner tracking system as its primary focus. One such sensor, the Circuit Exploratoire 65 nm (CE-65), and its evolution the CE-65v2, were developed to explore charge collection properties for varying configurations including collection layer process (standard, blanket, modified with gap), pixel pitch (15, 18, 22.5 pm), and pixel geometry (square vs hexagonal/staggered). In this work the characterisation of the CE-65v2 chip, based on Fe-55 lab measurements and test beams at CERN SPS, is presented. Matrix gain uniformity up to the O(5%) level was demonstrated for all considered chip configurations. The CE-65v2 chip achieves a spatial resolution of under 2 pm during beam tests. Process modifications allowing for faster charge collection and less charge sharing result in decreased spatial resolution, but a considerably wider range of operation, with both the 15 pm and 22.5 pm chips achieving over 99% efficiency up to a similar to 180 e(-) seed threshold. The results serve to validate the 65 nm TPSCo CMOS process, as well as to motivate design choices in future particle detection experiments.

The long term goal of the CERN Experimental Physics Department R&D on monolithic sensors is the development of sub-100nm CMOS sensors for high energy physics. The first technology selected is the TPSCo 65nm CMOS imaging technology. A first submission MLR1 included several small test chips with sensor and circuit prototypes and transistor test structures. One of the main questions to be addressed was how to optimize the sensor in the presence of significant in-pixel circuitry. In this paper this optimization is described as well as the experimental results from the MLR1 run confirming its effectiveness. A second submission investigating wafer-scale stitching has just been completed. This work has been carried out in strong synergy with the ITS3 upgrade of the ALICE experiment.

In this work the initial performance studies of the first small monolithic pixel sensors dedicated to charged particle detection, called CE-65, fabricated in the 65nm TowerJazz Panasonic Semiconductor Company are presented. The tested prototypes comprise matrices of 64 x 32 square analogue-output pixels with a pitch of 15 mu m. Different pixel types explore several sensing node geometries and amplification schemes, which allows for various biasing voltage of the detection layer and hence depletion conditions and electric field shaping. Laboratory tests conducted with a Fe-55 source demonstrated that the CE-65 sensors reach equivalent noise charge in the 15 to 25 e(-) range and excellent charge collection efficiencies. Charge sharing is substantial for standard diodes, but can be largely suppressed by modifying their design. Depletion of the thin sensitive layer saturates at a reverse diode bias of about 5 V.

SALT, a new dedicated readout Application Specific Integrated Circuit (ASIC) for the Upstream Tracker, a new silicon detector in the Large Hadron Collider beauty (LHCb) experiment, has been designed and developed. It is a 128-channel chip using an innovative architecture comprising a low-power analogue front-end with fast pulse shaping and a 40 MSps 6-bit Analog-to-Digital Converter (ADC) in each channel, followed by a Digital Signal Processing (DSP) block performing pedestal and Mean Common Mode (MCM) subtraction and zero suppression. The prototypes of SALT were fabricated and tested, confirming the full chip functionality and fulfilling the specifications. A signal-to-noise ratio of about 20 is achieved for a silicon sensor with a 12 pF input capacitance. In this paper, the SALT architecture and measurements of the chip performance are presented.

This paper presents the test-beam results of a monolithic pixel-detector prototype fabricated in 200nm Silicon-On-Insulator (SOI) CMOS technology. The SOI detector was tested at the CERN SPS H6 beam line. The detector is fabricated on a 500 mu m thick high-resistivity float-zone n-type (FZ-n) wafer. The pixel size is 30 mu m x 30 mu m and its readout uses a source-follower configuration. The test-beam data are analysed in order to compute the spatial resolution and detector efficiency. The analysis chain includes pedestal and noise calculation, cluster reconstruction, as well as alignment and eta-correction for non-linear charge sharing. The results show a spatial resolution of about 4.3 mu m.

The Silicon-On-Insulator (SOI) CMOS is one of the most advanced and promising technology for monolithic pixel detectors design. The insulator layer that is implemented inside the silicon crystal allows to integrate sensors matrix and readout electronic on a single wafer. Moreover, the separation of electronic and substrate increases also the SOI circuits performance. The parasitic capacitances to substrate are significantly reduced, so the electronic systems are faster and consume much less power. The authors of this presentation are the members of international SOIPIX collaboration, that is developing SOI pixel detectors in 200 nm Lapis Fully-Depleted, Low-Leakage SOI CMOS. This work shows a set of advantages of SOI technology and presents possibilities for pixel detector design SOI CMOS. In particular, the preliminary results of a Cracow chip are presented.

This paper presents the design of a new monolithic Silicon-On-Insulator pixel sensor in $200~nm$ SOI CMOS technology. The main application of the proposed pixel detector is the spectroscopy, but it can also be used for the minimum ionizing particle (MIP) tracking in particle physics experiments. For this reason few different versions of pixel cells are developed: a source-follower based pixel for tracking, a low noise pixel with preamplifier for spectroscopy, and a self-triggering pixel for time and amplitude measurements. In addition the design of a Successive Approximation Register Analog-to-Digital Converter (SAR ADC) is also presented. A 10-bit SAR ADC is developed for spectroscopic measurements and a lower resolution 6-bit SAR ADC is integrated in the pixel matrix as a column ADC, for tracking applications.

The aim of this work is to develop a dedicated low power transmitter interface for high-speed data transmission in CMOS 130 nm technology. Such interface is necessary in complex ASICs working at high frequencies and processing large amounts of data, in particular it is needed in advanced detector readout systems of particle physics experiments. New multichannel readout ASICs, capable to transmit data at high frequencies (>5Gb/s), with low jitter, and consuming very low power, are recently being intensively developed. A Current Mode Logic (CML) and Source-Series Terminated (SST) interfaces are natural candidates to drive the data out of the chip. A broadband extension techniques using inductors may be applied to extend the bandwidth of these drivers. Unfortunataly, inductors occupy very large area what limits their applications in ASICs. In this work the CML driver using inductive peaking and two SST drivers (with, without series peaking) were developed to achieve transmission speeds between 5-10 Gb/s, together with very low (<;2 ps) jittter. We present and compare the schematic and post-layout simulations of the developed drivers together with all relevant parameters (speed, jitter, eye diagram). Prototype designs in CMOS 130 nm were already submitted and are now in fabrication.

A stable reference voltage (or current) source is a standard component of today's microelectronics systems. In particle physics experiments such reference is needed in spite of harsh ionizing radiation conditions, i.e. doses exceeding 100 Mrads and fluences above 1e15 n/cm2. After such radiation load a bandgap reference using standard p-n junction of bipolar transistor does not work properly. Instead of using standard p-n junctions, two enclosed layout transistor (ELTMOS) structures are used to create radiation-hard diodes: the ELT bulk diode and the diode obtained using the ELTMOS as dynamic threshold transistor (DTMOS). In this paper we have described several sub-1V references based on ELTMOS bulk diode and DTMOS based diode, using CMOS 130 nm process. Voltage references the structures with additional PTAT (Proportional To Absolute Temperature) output for temperature measurements were also designed. We present and compare post-layout simulations of the developed bandgap references and temperature sensors, which show correct operation (<1mV bandgap stability, linear PTAT) in teperature range -20 to 100 celsius degree.

This paper presents some observations and ideas collected during the tests of the SOI sensors, based on the integration type pixels. First, it contains a rough analysis of the Correlated Double Sampling filtering properties with respect to different noise sources and long sampling intervals, which are typical for the pixels under consideration. Second, results of the pixel leakage current measurements in the pix_2012 and DIPIX pixel detector chips are presented.

This paper presents the design of the 10-bit Successive Approximation Register Analog-to-Digital Converter (SAR ADC) achieving 20 MHz sampling frequency at a power consumption of about 900 μW and 1.8 V power supply. The ADC was designed in 200 nm Silicon-On-Insulator (SOI) CMOS process. The SOI is one of the most advanced CMOS technology that allows to reduce the parasitic capacitances, limit power dissipation and increase speed of the system.