Using X-ray diffraction (XRD) technique, we have investigated the crystallinity of La- or Y-doped HfO2, formed with a capping process achieved by varying the crystallinity of the base-HfO2. In the capping process, high temperature annealing was performed after the deposition of La-oxide or Y-oxide on the base-HfO2. After the annealing, we found that the crystallinity of the La-doped HfO2 depended on the crystallinity of the base-HfO2, although the Y-doped HfO2 exhibits only a small dependency. To achieve crystalline La-doped HfO2 having higher-k with capping process, the base-HfO2 should be amorphous.

We studied the impact of Yttrium and Lanthanum incorporation into HfO2 on reliability (TDDB, PBTI and 1/f noise). They introduce smaller Weibull β values and early failure in TDDB, with negative shift in PBTI. They are caused by the negatively charged interstitial oxygen defect generated by Yttrium and Lanthanum incorporation. The effect of Lanthanum is larger than that of Yttrium. It can be explained by the larger ion radius and molecular volume of La2O3 than Y2O3. On the other hand, they are effective in noise reduction, as an effect of interface state density reduction. The key point in fabricating low Vth and highly reliable MOSFETs is the technology for suppression of this interstitial oxygen defect generation.

We have studied unusual V th shifts in the positive bias temperature instability (PBTI) and negative bias temperature instability (NBTI) of yttrium-doped HfO2 gate dielectrics. Both positive and negative stress conditions introduce shifts in opposite directions for yttrium-doped HfO2 in the low stress region. That is, a negative shift under a positive bias and a positive shift under a negative bias were observed. This is due to yttrium-related defects, with electron detrapping for PBTI and electron trapping for NBTI. Such defect formation can be suppressed by incorporating nitrogen into HfO2.

We have proposed a single metal/dual high- k gate stack for aggressively scaled complementary metal-insulator-semiconductor field-effect transistors (MISFETs). The threshold voltage is controlled by the dual high- k dielectrics, such as MgO- and Al 2 O 3 -containing HfSiON for n- and p-type MISFETs, respectively. The gate profile is precisely controlled by taking advantage of a common gate electrode, which will suppress the variation in device performance. Based on this device concept, we have actually fabricated W/TiN/HfMgSiON n-type MISFETs and W/TiN/HfAlSiO p-type MISFETs and have successfully demonstrated a low threshold voltage operation for both of n- and p-type MISFETs.

We have investigated the effect of postdeposition annealing (PDA) of Al2O3-capped HfO2 films on the flatband voltage (V-fb) shift and threshold voltage (V-t) variation in TiN gate p-type metal-insulator-semiconductor field-effect transistors (pMISFETs). We found that optimizing the PDA conditions to diffuse Al2O3 into the HfO2 films is a key factor for controlling V-fb, and high-temperature PDA immediately after Al2O3 deposition induces a positive V-fb Shift. Additional V-t variation was observed when the PDA temperatures after Al2O3 deposition were 850 and 950 degrees C. In contrast, a higher temperature PDA at 1050 degrees C after Al2O3 deposition can suppress V-t variation to almost the same level as that obtained in a HfO2 film without an Al2O3-cap layer, although the equivalent oxide thickness (EOT) increases. We also found that superior device characteristics, such as low V-t, suppression of V-t variation, and suppression of EOT increase, were obtained by performing PDA before Al2O3 deposition. (C) 2009 The Japan Society of Applied Physics

We studied the impact of Yttrium and Lanthanum incorporation into HfO2 on reliability (TDDB, PBTI and 1/f noise). They introduce smaller Weibull beta values and early failure in TDDB, with negative shift in PBTI. They are caused by the negatively charged interstitial oxygen defect generated by Yttrium and Lanthanum incorporation. The effect of Lanthanum is larger than that of Yttrium. It can be explained by the larger ion radius and molecular volume of La2O3 than Y2O3. On the other hand, they are effective in noise reduction, as an effect of interface state density reduction. The key point in fabricating low V-th and highly reliable MOSFETs is the technology for suppression of this interstitial oxygen defect generation.

Three SiN offset spacers were compared regarding the suppression of the gate-edge metamorphoses (GEMs) of scaled TaSiN/HfSiON n-type metal-oxide-semicondutor field-effect-transistors. The offset-spacer-induced GEM appears only in short-channel devices as a high threshold voltage (V(th)) and a parasitic resistance. On the basis of the device characteristics, the origin of GEMs was hypothesized to be the negative fixed charge in HfSiON on the gate edges. The low-temperature, Cl-free SiN offset spacer is promising for use in scaled metal/high-k devices because it provides the lowest Vth and the highest drivability, particularly in short-channel devices, by suppressing GEMs.

We will give practical and manufacturable solutions for metal gate/dual high-k CMOS fabrication processes with low threshold voltages which are suitable for scaled CMOS device manufacturing.

We investigated the controversial effective workfunction and electron mobility of TiN/HfSiON devices by intentionally adding MgO or La2O3 into HfSiON and by changing the material on TiN or the TiN thickness. As a result, we found a close relationship between the electron mobility at low effective field and the flatband voltage. This relationship is explained on the basis of the fixed charge in HfSiON and its neutralization. The intrinsic workfunction of TiN/HfSiON without charge is determined to be 4.3 eV from the flatband voltage when the electron mobility at low effective field is the highest. [DOI: 10.1143/JJAP.47.7780]

We have clarified that, in a metal/high-k gate stack, as well as the variability introduced by random dopant fluctuations (RDF), the threshold voltage variability (TVV) is attributable to the crystal structure and grain size in the metal gate. We have successfully eliminated this additional factor by reducing the grain size in the metal gate. We demonstrated that the incorporation of C into TiN metal gates transforms the crystalline film into an amorphous one, effecting a reduction in the TVV in HfSiON pFET devices. We observed that the TVV of C-incorporated TiN devices was dominated by RDF, indicating that the additional factor due to the metal gate had been diminished.

We have proposed single metal/dual high-k (SMDH) CMISFETs for aggressively scaled devices. The low threshold voltage (Vth) for n- and pMISFETs are obtained by the dual high-k gate dielectrics. The common gate stack for n- and pMISFETs (single metal) is expected to suppress the variation of gate profile. We have successfully demonstrated low-Vth operation of TiN/HfMgO nMISFETs and TiN/HfAlO pMISFETs that were fabricated in a gate first process flow. We also investigated the high-k-induced Vth variation that can be another origin of the Vth variation. As a result, we found that TiN/HfMgO nMISFETs and TiN/HfAlO pMISFETs do not suffer from high-k-induced Vth variation, but that TiN/HfLaO nMISFETs fabricated by our current process suffer from it. Therefore, we need to optimize the La incorporation process, such as, post-deposition anneal, in order to suppress local high-k-induced Vth variation for TiN/HfLaO nMISFETs.