In this work, body diode stress has been carried out for 1700 V 25 mΩ planar SiC MOSFETs. The epitaxial wafers were mapped with Infra-Red photoluminescence (IR-PL) to determine and localize the exact number of basal plane dislocations present in the drift layers of each die. The SiC MOSFETs were then packaged in groups with individual BPD counts in different bins ranging from 0 up to more than 30 per device. Pulsed body diode measurements with high currents of 250-400 A (about 1000-1600 A/cm 2 ) were then performed with electrical characterization before and after to check for drift in key electrical parameters. Significantly increased R DSon was found after high current stress from about 300 A for devices with BPDs. A physical analysis of the degraded devices by backside electroluminescence show the presence of several trapezoid-shaped patterns indicating the occurrence of bipolar degradation.

Gallium Oxide has undergone rapid technological maturation over the last decade, pushing it to the forefront of ultra-wide band gap semiconductor technologies. Maximizing the potential for a new semiconductor system requires a concerted effort by the community to address technical barriers which limit performance. Due to the favorable intrinsic material properties of gallium oxide, namely, critical field strength, widely tunable conductivity, mobility, and melt-based bulk growth, the major targeted application space is power electronics where high performance is expected at low cost. This Roadmap presents the current state-of-the-art and future challenges in 15 different topics identified by a large number of people active within the gallium oxide research community. Addressing these challenges will enhance the state-of-the-art device performance and allow us to design efficient, high-power, commercially scalable microelectronic systems using the newest semiconductor platform.

6" Silicon Carbide substrates contain more than 10000 crystal defects per cm 2 . A large fraction of those are embedded into active SiC device structures which may cause electrical failures, alter the device performance or significantly reduce the operating life time of individual devices. In this work we provide insights on cause and effect of several types of crystal defects and discuss approaches how to reduce their occurrence, investigate their degradation modes and strategies to eliminate affected dies.

The recent development and commercialization of wide bandgap (WBG) power semiconductors, specifically gallium nitride (GaN) and silicon carbide (SiC), have driven the increase in switching frequency for soft-switching power converters, such as the Class E, Class Φ 2 , and Class DE resonant inverters and rectifiers. However, prior literature has characterized numerous commercial GaN and SiC devices using the Sawyer-Tower circuit and discovered significant large-signal C oss charge-voltage hysteresis. This C oss hysteresis, equivalent to OFF-state energy loss, is highly dependent on the frequency and voltage across the device, hindering the efficiency and performance of MHz-range soft-switched converters. This article is the first to explain the origin of the C oss loss in SiC power devices as charging and discharging conduction losses at the termination of the device. The loss characteristics relative to the operating voltage, frequency, dV/dt, and temperature are dictated by incomplete ionization. Incomplete ionization also highlights a significant inconsistency between the large-signal C oss behavior and small-signal behaviors, which is often the model used in manufacturers' datasheets and SPICE simulations. The large-signal charge-voltage behavior is transient, where the charge in C oss depends on the rate of the voltage swing across the device. We validate these hypotheses through mixed-mode simulations using the Sentaurus technology computer-aided design (TCAD) and experimentally using commercial and custom SiC devices.

In this paper hybrid switches or later in the text referred as H-SW consisting either of high speed or low VCEsat Si IGBTs, connected in parallel with low current SiC MosFET, have been proposed as a novel approach to combine the best features of Silicon IGBTs and Silicon Carbide MosFET switches at the lowest possible costs. The requirements for lower losses and higher switching frequencies has led to the development of SiC devices, but their higher cost has slowed their adoption. In addition to the significant acceleration in switching speed, the SiC MosFET is able to lower the VCEsat and enables freewheeling through its body diode.

We report measurements of specific avalanche energies as function of time in avalanche, perform thermal analysis and verify the results by temperature-dependent UIS tests. We demonstrate that linear thermal analysis is inaccurate in application to UIS in SiC due to much higher critical temperatures in SiC as compared to silicon. An activation-type dependence with an apparent energy of 1.3 eV is established between time in avalanche and critical failure temperature. The failure mechanism for UIS is shown to be unrelated to electronic instability.

We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 °C. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To evaluate package level reliability, high temperature gate bias (HTGB) stress tests were conducted. Some samples failed in positive gate bias stress and more severe negative threshold voltage shift was observed in negative gate bias stress for the high temperature poly annealed condition.

Avalanche breakdown of novel 650 V SiC Schottky-barrier rectifiers is investigated. The rectifier diode has low leakage current for the temperatures up to 300 degrees C. Thermal coefficient of avalanche breakdown increases with the temperature to around 0.009%/K at 200 degrees C. Near-uniform avalanche breakdown is verified using emission imaging, and maximum specific avalanche energy of 20.7 J/cm(2) is achieved. The critical temperature for stability in unclamped inductive switching (UIS) is above 520 degrees C as estimated through thermal simulation. Longterm walkout of breakdown voltage at 176 degrees C is less than 0.02%.

1200V SiC MOSFETs with low on-resistance were fabricated on 6 inch wafers and characterized to assess the device ruggedness and reliability. TCAD simulations with oxide interface traps were performed and compared with the target device output characteristics with Rsp = 4.4 mOmega.cm2. To investigate the device ruggedness and oxide quality, wafer level unclamped inductive switching (UIS), gate oxide integrity (GOI), and time-dependent dielectric breakdown (TDDB) tests were conducted. In addition, positive and negative bias threshold voltage stress test and high temperature reverse bias (HTRB) stress test were performed to access the long term stability. Good avalanche ruggedness statistics and reliable oxide quality were shown and improved VTH stability during stress test was found compared to three similarly rated commercially available SiC MOSFETs.

Reliability characterization of SiC devices is an ongoing activity. For this work, 650 V SiC JBS diodes in TO247 housings were tested in H3TRB. After a test period of 4000 hours none of the devices had failed during the test and only two out of sixteen devices had failed during blocking curve measurements performed at intermediate time steps. This is significantly better performance than many silicon devices offer today. The failure spots of the failed devices were detected at the edge of the main junction appearing as semi-circular cavities in the aluminum metallization. All other devices did not even show deviations from their original blocking curves.

Reliability characterisation of SiC devices is an ongoing activity. For this work, four different splits of opened and gel-filled, 1200 V SiC MOSFETs in TO247 housings were tested in H³TRB for almost 2000 hours with monitoring of the leakage currents. In addition, electrical measurements and visual inspection were performed at intermediate time-steps. The objectives were investigating different passivation structures as well as the influence of a silicone gel encapsulation on the devices' humidity degradation.

SiC MOSFETs for 1200 V rating were fabricated and used for comparing electrical measurements with device simulations. The MOSFET subthreshold characteristic was used for tuning the simulation model parameters for acceptor interface traps at the SiC/SiO2 interface. Good agreement between measurements and simulations was obtained for ID-VGS, ID-VDS and breakdown voltage, whereas qualitative agreement was obtained for the reverse transfer capacitance and switching waveforms.

In this work, TCAD modeling of a 1200 V SiC MOSFET is presented. The main focus is on modeling of the channel mobility, and the Coulomb scattering by interface traps and surface roughness are therefore included. For the Coulomb scattering, the interface trap profiles have been extrapolated from the subthreshold characteristics at room temperature, whereas the scattering due to surface roughness has been fitted by comparing to the transfer characteristics at high gate bias. A comparison with measurements for the transfer characteristic and the output characteristic is also presented. Results show that the reduction of the threshold voltage with increasing temperature and the temperature dependence of the output characteristics are properly modeled.

This paper proposes a novel physical and scalable SPICE model for Silicon Carbide (SiC) power MOSFETs. The model is based on process and layout parameters, enabling design optimization through a direct link between SPICE, physical design, and process technology. One model applies to the entire technology instead of conventional discrete models for each device size and process variation. The SPICE agnostic model ports across multiple industry standard simulation platforms. The model has been validated with On Semiconductor's advanced 1200V SiC MOSFET technology.

Silicon carbide Schottky-barrier diode (SBD) rectifiers have been manufactured with low on-state voltages, high surge currents and high avalanche ruggedness. Non-destructive unclamped inductive switching currents of 188 A (mean) are achieved for the 1200 V 15 A rectifier. Very tight distribution of maximum sustained UIS current is confirmed. We relate improved avalanche ruggedness to bulk avalanche breakdown and show the breakdown pattern of the new Schottky rectifier being the same type as that for the p-n diode.

In this work, the detection and characterization of various crystal defects in high doped silicon carbide by photoluminescence (PL) is explored. The detection of basal plane dislocations in high doped epitaxial buffer layers is demonstrated using the near ultraviolet (NUV) spectra. Several characteristic defects in high doped 150mm substrates like grain boundaries and screw dislocations are also detected and characterized using the NUV PL spectra. Further characterization using molten potassium hydroxide etching is presented.

Silicon Carbide offers a compelling alternative for power devices. Its multiple uses in power efficient applications have led to a rush in commercialization of various device families. The major issues facing widespread adoption of SiC devices are cost and reliability. There are many facets to achieving and meeting consumer expectations in both these areas. One important part of reducing cost is moving to larger diameter substrates. This is currently challenging due to the lack of sufficient quality in 150mm wafers compared to 100mm wafers. Though quite some progress has been made on 150mm substrates, they still have a much larger number of crystal defects and macro defects than mature 100mm substrates. This leads to more concerns regarding reliability issues related to crystal defects in the substrates and subsequently in the epitaxial layers. This work focuses on ways of mitigating reliability issues while still leveraging the use of 150mm material. One facet of the reliability is dealing with defects that can cause bipolar degradation after stress [1,2]. These affect not just bipolar switches like BJTs but also the body diode of the MOSFETs. There are many approaches like buffer layers, pre-treatments, growth interrupts etc. to reduce these defects in the epi and prevent their propagation into the active layers. However some defects do make it through to the active layers. Traditional methods of detecting these defects like Basal Plane Dislocations (BPDs) are destructive in nature like molten KOH etching. Even this method is lacking since it only exposes the defects that break the surface of the epitaxial layers. Many of these BPDs can get converted to threading edge dislocations in the active regions and are therefore never detected by KOH etching. Recently many groups have started using Infra-Red Photoluminescence (IR PL) (700nm+) to detect both the basal plane dislocations and stacking faults [3-5] utilizing full wafer scans. In one of our previous works [6], we have used a similar method to screen out die that would exhibit degradation under forward bias stress. There are however some cases where the detection and screening using this method becomes challenging. This happens when the defects propagate in the buffer layer to just below or just into the active layer. This is because there is a lack of PL signal from the typically high doped buffer layers. This results in no signal or extremely faint PL signals coming from the buffer layers. As other research groups [7] have shown these defects in the buffer near the interface, have the tendency to expand into the active regions as a result of carrier recombination, thus killing or degrading the device performance. The solution to this problem is using the Near Ultra Violet PL spectrum to detect the crystal defects in the SiC material. The defects are detected as an absence of bandgap recombination spectra and thus detect any defects that cause non-radiative recombination. The BPDs are clearly detected even in highly doped buffer regions with sufficient SNR along with brighter features of the BPDs in the active layers. This stronger signal along with the longer overall length enables automated detection, classification and screening of the required defect types and provides visibility into the conversion efficiency of the buffer layers. This gives a very fast feedback path for epitaxial development to reduce the presence of these defects in the active regions. Traditionally a thorough feedback loop would involve fabricating and stressing PN diodes on the epi, which takes multiple weeks [6]. Other types of crystal defects like grain boundaries that are more prevalent in less mature 150mm substrates can also be detected using this method. This enables the identification of defective regions and defective wafer batches, thereby providing a fast and non-destructive feedback loop to the substrate vendors. A combination of these methods enables the confident use of 150mm substrates while maintaining the reliability expectations of the device customers. Results from improved quality epitaxial layers on both 100mm and 150mm substrates will be presented. Comparison and validation of the defect scan data to molten KOH etching will also be presented. [1] A. Agarwal et al. Mater. Sci. Forum, 527-529, pp1409-1412 (2006) [2] L. Farese et al. Mater. Sci. Forum, 645-648, pp1037-1040 (2010) [3] T. Tanaka et al. Mater. Sci. Forum, 778-780, pp91-94 (2014) [4] M. Odawara et al. Mater. Sci. Forum, 778-780, pp382-385 (2014) [5] S. Yamamoto et al. Mater. Sci. Forum, 778-780, pp951-954 (2014) [6] B. Buono et al. Mater. Sci. Forum, 778-780, pp1017-1020 (2014) [7] N. A. Mahadik et al. Appl. Phys. Lett. 100, 042102 (2012)

High avalanche robustness is achieved for unclamped inductive load conditions for silicon carbide Schottky diodes with nominal voltage and current rating of 1200 V and 15A. Mean avalanche energy is 0.38 J for a load of 0.02 mH and 0.62 J for 20 mH. Avalanche energy density exceeds 10 J per 1 cm2 of active device area. No change of breakdown voltage is observed for repetitive avalanche test until the diode destruction. The forward voltage drop tends to start increasing at around 77% of destructive avalanche energy.

Accurate characterization of discrete devices such as SuperFET(r), IGBTs and diodes is critical not only for the fine tuning and improvement of production processes, but also for the precise parameter extraction of advanced SPICE models. Among the many measureable parameters, the capacitive properties of a discrete device are of particular importance. In performing on-wafer high voltage capacitance measurements one has to overcome numerous obstacles. In particular CISS (CIES) presents multiple challenges in an on-wafer environment, due to the combination of the extracted gate to source (emitter) and gate to drain (collector) capacitances. In this paper we present the results of on-wafer high voltage measurements performed with a custom made setup. We describe in detail the necessary setup for obtaining highly accurate on-wafer measurements, and compare the results to measurements of packaged devices.