Charge pumping electrically detected magnetic resonance (CP-EDMR) has previously been demonstrated as a powerful characterization technique for performance-limiting point defects in 4H-SiC metal-oxide-semiconductor field-effect-transistors (MOSFETs). The detected CP-EDMR signal provides direct access to microscopic information about the recombination centers within the transistor gate inversion region. In this work we demonstrate how the CP-EDMR signal intensity changes under accelerated constant current gate stress for oxide fields above the impact ionization critical field. Our results demonstrate that gate stress not only creates positive charge trapping in the SiO2 but also induces non-recoverable point defects in the SiC/SiO2 near-interface.

Silicon carbide (SiC) metal-oxide-semiconductor field-effect-transistors (MOSFETs) enable high-voltage and high-temperature power conversion. Compared to Si devices, they suffer from pronounced gate leakage due to the reduced electron tunneling barrier at the interface between SiC and amorphous silicon dioxide (a-SiO_2). We develop a self-consistent, physics-based simulation framework that couples electrostatics, quantum tunneling, carrier transport, impact ionization, and charge trapping for both electrons and holes. The model quantitatively reproduces measured gate-current-voltage characteristics of SiC MOS capacitors over a wide temperature (80-573 K) range and a wide bias range without empirical fitting. Simulations reveal that conduction electrons in a-SiO_2 can trigger impact ionization, which generates electron-hole pairs, and leads to capture of holes in the oxide bulk, thereby enhancing gate leakage current. The framework captures these coupled processes across multiple orders of magnitude in time and field, providing predictive capability for oxide reliability. Although demonstrated for SiC devices, the methodology also applies to Si technologies that uses the same gate dielectric.

Charge pumping electrically detected magnetic resonance (CP-EDMR) has previously been demonstrated as a characterization technique for performance-limiting point defects in metal-oxide-semiconductor field-effect-transistors (MOSFETs). This Letter demonstrates the much-promised defect selectivity of CP-EDMR in a 4H-SiC n-channel MOSFET, differentiating between two distinct paramagnetic centers based on the kinetic properties, following from variation of the experimental CP parameters. The centers are shown to differ both in their characteristic g-shifts and in hyperfine interactions with surrounding nuclei. In addition, we show that under magnetic resonance conditions these two defects show opposite effects on the CP current, which results in a sign inversion of the CP-EDMR spectrum. For one defect, which only appears under relatively low-frequency CP-excitation, the microwaves induce a decrease in CP-current, while the other defect shows an increase at all applied CP-frequencies. Starting from an empirical CP model, we demonstrate that an enhanced efficiency of carrier capture or emission leads to either an increase or a decrease in the CP current, respectively. Simulations based on this model qualitatively reproduce the observed dependencies of the CP-EDMR signal on CP bias voltage and excitation frequency.

This paper provides a status overview of both intrinsic and extrinsic gate oxide reliability on SiC MOSFETs. Forward gate bias TDDB data is used to extract the time-to-fail of the intrinsic population. In addition, from the Ig-t characteristics during TDDB stress, a “safe-operation area” can be extracted. Similarly, device lifetime under reverse bias stress (“accelerated reverse bias”) is determined and compared to the FIT rate under Cosmic Ray Irradiation. Finally, the extrinsic failures of SiC MOSFET is addressed. The field acceleration factor for extrinsic failure is found to be lower than for intrinsic failure. The statistical treatment for field return rate extraction is outlined.

SiC power MOSFETs are reported to suffer from both positive and negative threshold voltage shifts. Positive shift is well understood in the literature and attributed to electron trapping in near interface oxide traps (NIOTs). Negative shift is explained by hole generation and trapping in the oxide via impact ionization favored by the strong oxide field. However, studies on negative shift are still ongoing, and the origin and nature of the process are not fully understood. This study advances the comprehension of negative threshold voltage shift by investigating MOS capacitors subject to positive bias stress. We demonstrate that: a) a significant negative threshold shift is observed when the electric field is greater than 7.5 MV/cm; b) the detected shift is not recoverable at zero bias. Recovery can be obtained only by applying a positive gate voltage indicating a field-driven detrapping process. c) Trap-state mapping measurements were carried out to extract the activation energy of the detrapping processes, and a weak thermal activation was observed. Results collected within this paper indicate that holes are trapped at deep centers, and thermal detrapping is not possible. Hole release is only possible when a high field is applied to the insulator, possibly due to the recombination between leaking electrons and trapped holes.

This work improves the understanding of charge trapping in SiC MOSFETs during constant gate current stress, by presenting an analysis based on charge pumping measurements (constant-amplitude approach) and threshold voltage measurements. The tests were done by a custom-made, on-wafer, in situ monitoring setup. A non-monotonic trend for the gate voltage was observed during the stress, and each phase was linked to a charge trapping mechanism: a) electron trapping at near-interface oxide traps; b) hole trapping, due to impact ionization in the oxide; c) generation of electron traps at the interface. Charge pumping measurements provided a quantitative description of the variation of the interface traps in the long term. Such trapping phenomena are explained based on the literature on interface and oxide defects in SiC. Persistence of the created defects and trapped charge was studied as well.

Abstract. Integration of microwave sources and detection circuits has led to the design of very compact electron paramagnetic resonance (EPR) instruments, so-called EPR on-a-chip (EPRoC). As recently demonstrated, this approach also offers opportunities for electrical detection of magnetic resonance (EDMR), a variant of EPR in which the magnetic resonance effect is detected via changes in the electrical properties of materials or devices. Here, we report the demonstration of EDMRoC on lateral SiC MOSFETs under charge pumping (CP) conditions. The detected CP current gives direct access to microscopic information about the recombination centers within the transistor gate inversion region under the gate dielectric. Efficient and selective microwave excitation of the region of interest of the device can be obtained by only modest modifications to both the MOSFET and the EPRoC electronic board. A comparative study between EDMRoC and a traditional resonant cavity configuration reveals comparable signal-to-noise ratios for CP-detected EDMR spectra. In addition to space- and cost-efficiency, EDMRoC offers alternative detection modes with scanning and modulation of the microwave frequency, as well as potentially easier sample mounting and exchange. We end with a discussion of the advantages, limitations, and perspectives of the EDMRoC set-up compared to EDMR in a conventional EPR spectrometer.

This paper provides a status overview of SiC transistor reliability, with focus on a commercially released planar gate technology with a thermally grown gate oxide. Gate dielectric lifetime from time dependent dielectric breakdown (TDDB), lifetime under reverse drain bias, susceptibility to single event burn-out under neutron irradiation, bias temperature instability (BTI), gate switching instability (GSI), and bipolar degradation are discussed. Experimental data, modeling and lifetime projections are provided with a focus on automotive traction applications.

Device lifetime under reverse bias conditions is an important reliability concern for SiC devices. Provided that the termination structure is well designed, device failure in the active cell is driven by gate oxide breakdown due to the high field in the semiconductor and gate dielectric. For planar MOSFETs, the largest field occurs in the JFET region [1,2]. Standard HTRB testing is insufficient to estimate failure rates under operating conditions and hence testing under accelerated off-state conditions (ALT-HTRB) is required. This paper provides data, statistical analysis, failure analysis and finally a Weibull statistics-based temperature, Vd and stress time dependent model.

This paper introduces a novel three-dimensional approach to model threshold voltage variation (Delta V-th) during time-dependent dielectric breakdown (TDDB) stress of SiC trench MOSFETs in a wide temperature range T=0 ... 250 degrees C and studies the processes of Delta V-th recovery at room temperature.

This paper introduces the concept of safe operating area (SOA) for the gate dielectric of SiC MOSFETs. The SOA is defined as the stress time-field-temperature space in which the transistor will remain within datasheet specifications and is a more useful parameter than the standardly reported time-to-failure (tfail). Using Weibull statistics, the SOA at 5ppm, 20 Years, T=175°C is ~V gs =21.5V for onsemi SiC MOSFET products.

Unexpected behavior is observed when charge pumping is performed on silicon carbide MOSFETs with a thermally grown silicon dioxide gate dielectric. Supported by experimental evidence, two root causes are proposed: the trap density and the channel non-equilibrium. These are difficult to overcome experimentally due to limitations by oxide breakdown and doping variation along the channel, respectively. A correct interpretation then requires a 2D model.

The continual improvement of GaN-on-Si processes motivates the integration of more complex circuits alongside GaN power devices. Additional transistors can be leveraged to provide control, logic, and protection; however, low-voltage GaN devices consume more power and area than similar CMOS counterparts. This article investigates the feasibility of a monolithic gate-monitoring circuit integrated with a GaN power device and gate driver. The monitoring circuit captures 16 samples within 50 ns during the gate rising transient and stores them in on-chip capacitors. The stored voltages are asynchronously read off-chip through integrated source-follower buffers and a digitally controlled multiplexer. The proposed design incorporates approximately 330 e-HEMT transistors and was fabricated in a 200-V GaN-on-SOI process. A detailed characterization was performed to calibrate the dynamic on-chip gate voltage from the sampled values that are read off-chip, paving the way for future active control based on this feedback. Experimental results and the postcalibration estimate of the on-chip gate voltage highlight that off-chip measurements are poor and pessimistic estimators for the on-chip dynamic excursions. The on-chip gate-voltage waveform was estimated using the sampling circuit while switching the power device at 80 V, 1.5 A, demonstrating more accurate measurements of on-chip signals. This circuit stands as a proof-of-concept for the viability of integrating relatively complex circuits in GaN power ICs to perform critical monitoring and sensing tasks.

We investigate and model the threshold voltage instabilities of 4H-SiC power MOSFETs at room and cryogenic temperatures, based on wide time range (from µs to ks) PBTI analysis. We show that for T > 200 K a stretched (log-like) de-trapping transient dominates the recovery kinetics, while at lower temperatures (down to 80 K) a fast exponential component is also visible. The charge de-trapping process is modeled as a distribution of traps spread over the midgap, that causes the threshold instability. Results indicate: i) one narrow gaussian energy distribution at the interface, visible at low temperature, which explains the exponential transient behavior for T < 200 K; ii) a broader distribution deeper in energy, that is considered to take into account the logarithmic de-trapping kinetics at higher temperatures and the threshold static shift with temperature. The proposed modeling framework can accurately reproduce the experimental results.

Gallium Oxide has undergone rapid technological maturation over the last decade, pushing it to the forefront of ultra-wide band gap semiconductor technologies. Maximizing the potential for a new semiconductor system requires a concerted effort by the community to address technical barriers which limit performance. Due to the favorable intrinsic material properties of gallium oxide, namely, critical field strength, widely tunable conductivity, mobility, and melt-based bulk growth, the major targeted application space is power electronics where high performance is expected at low cost. This Roadmap presents the current state-of-the-art and future challenges in 15 different topics identified by a large number of people active within the gallium oxide research community. Addressing these challenges will enhance the state-of-the-art device performance and allow us to design efficient, high-power, commercially scalable microelectronic systems using the newest semiconductor platform.

GaN power high-electron-mobility transistors (HEMTs), with their fast switching transients and poor overcurrent tolerance, require overcurrent protection (OCP) circuits that can respond in under $\text{0.5}\, \mu \text{s}$ . Monolithically integrating digital and analog circuits with GaN power devices is enabled by recent advancements in high-voltage GaN integrationplatforms. Thus, integrated OCP designs can be used to reduce the protection response time, the area penalty, and the assembly complexity. This work presents the first fully integrated, senseHEMT-based GaN OCP integrated circuit (IC) with an adjustable current limit and programmable blanking time, suitable for a wide range of power applications. The IC, implemented on a 200-V GaN-on-Silicon-on-Insulator (GaN-on-SOI) process, contains a power HEMT with a senseHEMT for current sensing, a totem-pole-based gate driver, an analog comparator, and a set of logic circuits to enable high-speed closed-loop OCP. The fabricated design is tested in both a clamped switching setup and a 12–48 V boost converter. The minimum OCP response time is estimated to be 36 ns with $dI_{D}/dt\geq \text{30}\,\text{A}/\mu \text{s}$ , one of the fastest amongst state-of-the-art OCP circuits for GaN.

We investigate the effect of Negative-Bias-Temperature-Instability on 4H-Silicon Carbide MOSFETs at room and cryogenic temperature and found a large negative threshold voltage shift at T < 250 K. For T < 140 K, both capture and emission follow an almost ideal exponential transient. Cryogenic temperatures reveal fast interface traps, otherwise difficult to probe at relatively high temperatures; we attribute the threshold voltage shift to a high density of hole traps located: 1) close to the SiC valence band and able to emit within the measurement time window; 2) above the SiC valence band, responsible of the slow transient at low temperature. Finally, the extraction of the emission time constant via Capture Emission Time map analysis allowed to extract the activation energy of mechanism 2 (82 meV).

Similar charge to failure distributions with mean values of about 50 C/cm 2 were measured for planar SiC MOSFETs and MOS capacitors. Fast occurring and saturating negative flatband and threshold voltage drops were found in time resolved 1 second long pulsed gate current stress with I G =1 mA/cm 2 at T=150 °C. No substantial difference in V TH drift rate with V GS =28 V at T=150 °C was found after about 10 s recovery period for I G stressed devices compared with unstressed devices. Additionally, I G stressed and unstressed devices did not differ in final V TH shift at T=25 °C after V GS =28 V stress (during 3 hrs or 31 hrs). More gate oxide reliability characterization is important to determine if 1 mA/cm 2 pulsed gate current stress creates any permanent changes to the SiC MOSFET device behaviour. Additionally, parametric shifts in V TH and R DSon was examined after long-term AC gate bias stress by a gate driver switching between-8V and 20V for four different commercially available SiC MOSFETs.

Precise control of the applied gate voltage is essential for GaN HEMTs as the margin between their recommended and maximum gate voltages can be as low as 1V. This work presents a GaN power IC with a driver that samples the duration of gate overvoltage during turn-on transients. The overvoltage detection circuitry compares the on-chip gate voltage of the power device with an externally-set reference. During a gate overvoltage event, a pre-charged hold-capacitor is discharged, with the final capacitor voltage indicating the total overvoltage duration. With this single-die solution, the overvoltage period can be measured without the distortion that occurs when observing a high $dv/dt$ signal through bond wire and PCB parasitic elements. The overvoltage detection circuitry is fabricated in a 200-V GaN-on-SOI process alongside an $80-\mathrm{m}\Omega$ e-HEMT with an integrated gate driver. Experimental characterization shows that the change in capacitor voltage is a strong predictor of the overvoltage duration, paving the way for using such a system for optimization in active gate drive scenarios.

Similar charge to failure distributions with mean values of about 50 C/cm2 were measured for planar SiC MOSFETs and MOS capacitors. Fast occurring and saturating negative flatband and threshold voltage drops were found in time resolved 1 second long pulsed gate current stress with IG=1 mA/cm2 at T=150 °C. No substantial difference in VTH drift rate with VGS=28 V at T=150 °C was found after about 10 s recovery period for IG stressed devices compared with unstressed devices. Additionally, IG stressed and unstressed devices did not differ in final VTH shift at T=25 °C after VGS=28 V stress (during 3 hrs or 31 hrs). More gate oxide reliability characterization is important to determine if 1 mA/cm2 pulsed gate current stress creates any permanent changes to the SiC MOSFET device behaviour. Additionally, parametric shifts in VTH and RDSon was examined after long-term AC gate bias stress by a gate driver switching between-8V and 20V for four different commercially available SiC MOSFETs.