The semiconductor industry is experiencing a transformative phase driven by the adoption of AI, purpose-built hardware in data centers, high-performance computing, and edge computing. However, traditional lithographic scaling of transistors is facing diminishing returns in performance improvements. Chip designs are nearing or surpassing the maximum size of a single scanner field, presenting a challenge for manufacturers. Chiplet integration emerges as a solution, breaking down complex chips into modular chiplets for enhanced flexibility, yield, economics, and scalability. Advanced packaging technologies play a crucial role in enabling seamless inter-chiplet communication. Multibeam Corporation's Multicolumn Electron Beam Lithography (MEBL) system offers a solution for patterning substrates in large multi-chip module assemblies, revolutionizing direct-write patterning systems with high productivity. This paper explores how MEBL is creating game-changing improvements in wafer-scale interposers (up to >80× larger), adaptive patterning (>10× higher bandwidth), and on-wafer die-die stitching (stitched die transcending reticle limit, with >98% energy reduction per bit transfer). These innovations enable unmatched performance, cost, and scalability, driving innovations in advanced integration of chips.

Currently running at volumes in the millions of units per day on 300mm round format, Deca’s M-Series™ fan-out PLP technology and Adaptive Patterning® are being scaled up at ASE to 600 mm for production. The SEMI standard 600 mm square format pioneered by Deca, provides a 500% increase in usable area per panel providing cost-effective capacity growth as well as a powerful platform for high density integration of multi-die and chiplets in 2D, 2.5D and 3D structures. Deca’s patented Adaptive Patterning® coupled with chip attach compensation modeling overcomes the yield challenges associated with scaling to 600 mm and mitigates the compounding risk associated with the growing number of dies in a package, which is of particular importance for chiplet designs. The use of Laser Direct Imaging (LDI) overcomes the need for reticle stitching and eliminates this barrier for large package body sizes. In addition, 600mm allows for higher efficiency in terms of package count per format area over 300mm round, leading to less waste, thus a lower cost and a more environmentally friendly process. Recent advancements in LDI have allowed the potential to scale the technology to ultra-high density 2µm line & space redistribution layers (RDL) and 5μm vias. Advancement in Adaptive Patterning have led to multi-die packaging solutions without the need for complicated embedded bridge chips. With these ultra-high-density tools at hand, a breakthrough in device interface pitch of 20µm area array for leading edge silicon nodes will be outlined.

Our industry has entered the chiplet era where scaling and performance improvements are enabled through the heterogenous integration of various functions and wafer fab technology nodes through advanced packaging technology. Deca's M-Series™ is a chips-first, face-up FOWLP (fan-out wafer level packaging) technology which includes a highly planar surface for RDL build-up where the semiconductor device active surface and vertical sidewalls are fully encapsulated with an epoxy molding compound (EMC) or other dielectric material. Through scaling to 2µm lines & spaces and multiple redistribution layers (RDL), the M-Series provides powerful new possibilities for chiplet-based architectures moving to higher bandwidth interfaces where designers favor multiple parallel interconnects over classic SERDES connections. The desire for thousands of chiplet-to-chiplet connections is driving an unprecedented need for shrinking the device bond pad pitch especially for applications such as high-performance computing. A major barrier in shrinking the device bond pad pitch is die shift. Die shift is the natural variation in die location within an embedded structure stemming from chip attach, molding, and other process variables. Chips-first fan-out technologies using conventional design methods and mask-based lithography run into barriers in the range of 45µm device bond pad pitch due to the need for large capture pads which account for typical die shift. The M-Series overcomes die shift using Adaptive Patterning® (AP) with its unique design-during-manufacturing methods and mask-less laser direct imaging (LDI) photolithography. AP enables a precise RDL via connection to each device bond pad or additional layer by precisely aligning a unit-specific pattern to every device. The second-generation M-Series with Adaptive Patterning, or Gen 2, opens up an unprecedented 20µm area array pitch bond pads as a starting point with a roadmap to achieve 10µm bond pad pitch in the near future. In this paper, we will discuss preliminary Gen 2 design rules and their implementation on a test vehicle jointly produced by Deca and nepes hayyim. The test vehicle has two Chips First chiplet processors and four simulated footprints for high bandwidth memory (HBM) modules which would be mounted Chips Last. In order to enable ultra-high-density interconnect on Gen 2, the design rules allow for a 20µm device bond pad pitch and 2µm lines & spaces. The design and construction of the Gen 2 test vehicle will be examined.

This chapter describes the features of M-Series as a chip-first face-up fan-out wafer-level packaging (FO-WLP) technology that provides several important reliability and manufacturing benefits compared to traditional WLP and conventional fan-out packaging technologies. The key bill of material for the FO-WLP is the granular epoxy molding compound. In summarizing the market, front-end chip and system scaling will continue to require new creative breakthroughs in chiplets and heterogeneous integration, which continue to drive strong interest in advanced fan-out technologies such as M-Series with adaptive patterning (AP). In combination with AP, the design rules for M-Series provide the largest via contacts on the smallest chip interconnects. This is also described in this chapter. A detailed description of AP and how it supports high-density applications are also provided. The chapter describes scaling of M-Series for high-density integration.

Achieving the highest performance levels through heterogeneous integration requires innovation throughout the package design, layout, and manufacturing processes. As part of a recent partnership, Cadence and Deca have collaborated on a novel multi-chip(let) high-density RDL packaging solution based on Adaptive Patterning™ technologies. This approach removes several design hurdles for multi-chip(let) ultra-high-density fanout packages while providing a cost-effective alternative to foundry-based solutions. The Adaptive Alignment™ design technique translates and rotates polymer and copper routing layers to align with individual chip(let) locations precisely. Another technique, Adaptive Routing™, allows the designer to create dynamic regions within Cadence Allegro® Package Designer where layout features are automatically generated in real-time to create unit-specific patterns aligned with the actual location of each chip(let) pin. With the freedom to choose any combination of these Adaptive Patterning design methods, the designer is empowered to layout complex multi-chip(let) high-density fan-out packages while being assured that all normal variations in manufacturing can be accommodated based on certified design rules from Deca®. This presentation highlights ultra-high-density RDL layout of single-chip and multi-chip(let) designs using Deca Adaptive Patterning technology embedded in Cadence Allegro Package Designer, Silicon Layout Option. This paper includes showing the Cadence design tool flow for importing user data and configuring the Cadence database for M-Series™ FX fan-out designs.

The semiconductor industry has entered a new era where monolithic integration cannot achieve the economic gains of silicon scaling. The role of chiplets is crucial in this new era by enabling cost reduction through the heterogenous integration of various functions and wafer fab technology nodes. Deca's planar M-Series™ surface is ideal for building highly integrated fan-out SoC (System on Chip) structures. Scaling to 2μm lines & spaces and multiple redistribution layers (RDL) provides powerful new possibilities for IC designers. Chiplets can now be fabricated using the optimum wafer fab technology node providing the best performance with the most desirable commercial terms. In combination with Adaptive Patterning™, design rules for M-Series provide large via contacts on fine pitch chip interconnects. The scaling of M-Series for chiplets will be presented in this paper. The 2nd generation of M-Series starts with 2μm lines & spaces using laser direct imaging (LDI) with up to four layers of Cu RDL delivering die to die interconnect of >200 wires/mm/layer. This breakthrough in high-density routing is achieved on a simple molded chips-first, chips-up structure without the need for complicated bridge chips in substrates. We will also present a breakthrough in device interface density with 20μm pitch full array bond pads made possible with Adaptive Patterning (AP). This paper details the M-Series multi-chiplet fan-out structure with four Cu routing layers, all layers include 2μm lines & spaces fabricated using LDI and Adaptive Patterning. The M-Series fan-out structure readily supports through-mold Cu posts if a 3D package on package (3D PoP) structure is required.

Fan-Out Wafer Level Packaging (FOWLP) holds immediate promise for packaging semiconductor chips with higher interconnect density than the incumbent Wafer Level Chip Scale Packaging (WLCSP). FOWLP enables size and performance capabilities similar to WLCSP, while extending capabilities to include multi-device system-in-packages. FOWLP can support applications that integrate multiple heterogeneously processed die at lower cost than 2.5D silicon interposer technologies. Current industry challenges with die position yield after die placement and molding result in low-density design rules and the high-cost of accurate die placement. Efficiently handling die shift is essential for making FOWLP cost-competitive with other technologies such as FCCSP and QFN. This presentation will provide an overview of Adaptive Patterning, a new technology for overcoming variability of die positions after placement and molding. In this process, an optical scanner is used to measure the true XY position and rotation of each die after panelization. The die measurements are then fed into a proprietary software engine that generates a unique pattern for each package. The resulting patterns are dispatched to a lithography system, which dynamically implements the unique patterns for all packages within a panel. For system-in-packages, this process offers a unique advantage over a fixed pattern: each die shift can be handled independently. With a fixed pattern, the design tolerances need to be large enough for all die to shift in opposing directions, otherwise yield loss in incurred. With Adaptive Patterning, vias and RDL features remain at minimum size and are matched to the measured die shift. The die-to-die interconnects are dynamically generated and account for the unique position of each die. Thus, Adaptive Patterning retains the same high-density design rules regardless of how many die are in a package. Adaptive Patterning provides the capability to use high-throughput die placement to drive down cost, while enabling higher-density system-in-package interconnect. With this technology the industry can finally realize the cost, flexibility, and form factor benefits of FOWLP.

Fan-Out Wafer-Level Packaging (FO-WLP) holds immediate promise for packaging semiconductor chips for mobile consumer electronics applications. FO-WLP enables size and performance capabilities similar to Wafer-Level Chip-Scale PAcakging (WLCSP), while extending the capabilities to include multi-device system-in-packages. With lower costs than 2.5D interposer technologies, FO-WLP can support applications that integrate multiple die and devices from heterogenous processes. FO-WLP also provides a path for shrinking die geometries without driving printed circuit boards to smaller interconnects. Industry challenges in handling cost, yield, and the requirement for high die location accuracy after placement and molding have driven innovative approaches, such as Adaptive Patterning. Adopting these new technologies for single-die and system-in-packages will require more advanced design methodologies and tools than traditionally used in semiconductor packaging. This paper describes a new technology, called Adaptive Patterning, for overcoming the die-shift challenge. In this manufacutring process, an optical scanner is used to measure the true position of each die after molding, and a uniquely generated fan-out design is applied to each package. One design technique, adaptive alignment, shifts and rotates the first via and RDL layer to match the die location. Another technique, adaptive routing, utilizes a fan-out RDL design with sections removed near vias that contact the die. The final RDL connections to the die are generated by an auto-router after the true die locations are known. This technique requires that the design is routable for all permutations of die-shift and rotation. For designs containing multiple die or devies such as system-in-packages, both design techniques can be combined. In one example, two sections of via and RDL paterns were separately aligned to two die. Connections between the RDL patterns were completed by an auto-router to handle simultaneous worst-case shifts from both die. In all techniques, the design rules are parameterized by the radial shift, a value combining the X, Y, and rotation shift components into a single magnitude. The radial shift depends on the design technique, package size, and the offset of the die from package center. During the design process, this value can be computed from empirically gathered data. This paper details these design techniques and the parame-terization of design rules using the radial shift.

This work investigates the effects of after-the-fact chemical modification of a state-of-the-art commercial carbon-supported PtRu catalyst for direct methanol fuel cells (DMFCs). A commercial PtRu/C (JM HiSPEC10000) catalyst is post-doped with nitrogen by ion-implantation, where "post-doped" denotes nitrogen doping after metal is carbon-supported. Composition and performance of the PtRu/C catalyst postmodified with nitrogen at several dosages are evaluated using X-ray photoelectron spectroscopy (XPS), rotating disk electrode (ROE), and membrane electrode assemblies (MEAs) for DMFC. Overall, implantation at high dosage results in 16% higher electrochemical surface area and enhances performance, specifically in the mass transfer region. Rotating disk electrode (RDE) results show that after 5000 cycles of accelerated durability testing to high potential, the modified catalyst retains 34% more electrochemical surface area (ECSA) than the unmodified catalyst. The benefits of nitrogen post-doping are further substantiated by DMFC durability studies (carried out for 425 h), where the MEA with the modified catalyst exhibits higher surface area and performance stability in comparison to the MEA with unmodified catalyst. These results demonstrate that post-doping of nitrogen in a commercial PtRu/C catalyst is an effective approach, capable of improving the performance of available best-in-class commercial catalysts. (C) 2013 Elsevier B.V. All rights reserved.

This work illustrates the utility and improved performance of nitrogen-modified catalyst supports for direct methanol fuel cell (DMFC) applications. A unique two-step vapor-phase synthesis procedure is used to achieve the N-modification and Pt-Ru decoration of high surface-area carbon powders relevant to integration as electrocatalysts in fuel cell membrane electrode assemblies (MEA's). First, nitrogen surface moieties are incorporated into a commercial high surface area carbon support via a N-ion implantation technique, followed by Pt-Ru nanoparticle deposition via magnetron sputtering. The nitrogen-ion implantation of high surface area carbon supports yields superior Pt-Ru catalyst particle stability and performance as compared to industry standards. Specifically, results indicate a higher retention of metal catalyst surface area and electrochemical activity after accelerated electrochemical degradation testing. Further, characterization of catalyst materials before, during and after the electrochemical cycling provides insight into the catalyst particle coarsening and/or catalyst surface area loss mechanisms that dominate this fuel cell catalyst system. (C) 2013 The Electrochemical Society. [DOI: 10.1149/2.062304jes] All rights reserved.

Nitrogen functionalities significantly improve performance for metal-based carbon-supported catalysts, yet their specific role is not well understood. In this work, a direct observation of the nanoscale spatial relationship between surface nitrogen and metal catalyst nanoparticles on a carbon support is established through principal component analysis (PCA) of electron energy loss spectral (EELS) imaging datasets acquired on an aberration-corrected scanning transmission electron microscope (STEM). Improved catalyst–support interactions correlated to high substrate nitrogen content in immediate proximity to stabilized nanoparticles are first demonstrated using model substrates. These insights are applied in direct methanol fuel cell prototypes to achieve substantial improvements in performance and long-term stability using both in-house and commercial catalysts doped with nitrogen. These results have immediate impact in advanced design and optimization of next generation high performance catalyst materials.

In situ small-angle x-ray scattering (SAXS) is used to investigate the electrochemical durability of Pt-Metal (Pt-M) catalysts sputtered onto nitrogen-modified high surface area carbon powder. The results demonstrate that nitrogen modification promotes catalyst durability through reduction of nanoparticle dissolution and coarsening. Although particle sizes of Pt-M on high surface area carbon supports can be difficult to determine with transmission electron microscopy (TEM), a novel SAXS method has been employed to calculate particle size. SAXS analysis shows that the Pt-M nanoparticle size distribution remained stable for 3000 electrochemical cycles after nitrogen modification, whereas the unmodified support material leads to Pt-M nanoparticle instabilities. These results for industrial-relevant catalyst/support architectures underscore the potential of nitrogen-modified carbon support structures for enhanced Pt-M catalyst durability.

Non-Pt based oxygen reduction catalyst H-2-air fuel cell performance is reported for various electrode compositions. Ink formulations for pyrolyzed Co porphyrin based cathode electrocatalysts were evaluated in a membrane electrode assembly (MEA) configuration and X-ray photoelectron spectroscopy was performed on the MEA catalyst layers. The effect of cooling time trajectories of the catalysts after pyrolysis as well as Nafion content in the ink formulation were studied. By building statistical structure-to-property relationships between XPS and MEA performance using multivariate analysis we have determined that the higher stability of fast-cooled containing inks is mainly associated with better preserved graphic carbon from the carbon black and C-F moieties of the Nafion, while better MEA performance is a result of the presence of these moieties as well as pyridinic nitrogen and nitrogen associated with metal in the pyropolymer. Optimal Nafion content is determined at 1:1 catalyst:Nafion weight ratio, while higher Nafion concentrations causes oxidation of the Nafion backbone itself as well as leaching of the CoxOy particles from the catalyst and formation of oxidized species of Co, 0, C and F. Further, we report 1500 h of continuous fuel cell operation for two different non-platinum cathode catalysts in the optimized MEA. (C) 2012 Elsevier B.V. All rights reserved.

Commercialization of direct methanol fuel cells (DMFC) greatly depends on significant further improvements in catalytic activity and durability. Improved utilization of the noble metal catalysts, such as Pt and Ru is particularly critical to ensure further development of the technology. One very attractive approach that could potentially address these catalyst activity and durability issues is to improve catalyst-support interactions through the introduction of a dopant such as nitrogen [1, 2, 3]. A majority of the work using N-doped supports has been focused on Pt catalysts for hydrogen fuel cells. In this talk, we will discuss our recent findings using Nfunctionalized supports for Pt-Ru catalysts.

Electrochemical performance and durability of PtRu supported on N-doped Vulcan is evaluated as an anode in membrane electrode assembly (MEA) single-cell direct methanol fuel cell (DMFC) studies. This material is compared to two reference materials, an in-house PtRu catalyst supported on undoped Vulcan, prepared under the same conditions as the N-doped material besides doping, and a commercial PtRu/C (JM5000). Durability was tested out to 645 h, with periodic interruption for electrochemical testing. After durability, the MEA with N-doped PtRu/C retained more electrochemically active metal on the anode than the MEAs with commercial PtRu/C and undoped PtRu/C (124 compared to 106 and 82 cm(2) anode active area per cm(2) geometric surface area, respectively). From cathode CO stripping experiments and SEM-EDS studies, it was determined that the MEA with the undoped PtRu/C anode has twice as much ruthenium crossover as the MEA with the N-doped PtRu/C anode. Overall, the MEA with N-doped PtRu/C demonstrates significantly better methanol:air polarization performance compared to the MEA with undoped PtRu/C, and performs comparably to the MEA made with the commercial PtRu/C. The increase in durability for the MEA with the N-doped anode is attributed to nitrogen doping mitigating both anode metal dissolution and Ru crossover. (C) 2012 Elsevier By. All rights reserved.

This article reports the synthesis and performance of unsupported Ni(1-x)Zn(x) electrocatalysts for the oxidation of hydrazine in alkaline media. Characterization of these catalysts was achieved using XRD, SEM, and TEM to confirm phase compositions, crystal structures, and morphologies. High performance was observed for the α-Ni(0.87)Zn(0.13) and β(1)-Ni(0.50)Zn(0.50) electrocatalysts with an onset potential of -0.15 V (vs. RHE) and a mass activity of 4000-3800 A g(cat)(-1) at 0.4 V (vs. RHE), respectively. Additionally, in situ IRRAS studies were conducted to understand the mechanism of oxidation. These results demonstrate the feasibility of Ni(1-x)Zn(x) catalysts for direct hydrazine anionic fuel cells.

Modification of physiochemical and structural properties of carbon-based materials through targeted functionalization is a useful way to improve the properties and performance of such catalyst materials. This work explores the incorporation of dopants, including nitrogen, iodine, and fluorine, into the carbon structure of highly-oriented pyrolytic graphite (HOPG) and its potential benefits on the stability of PtRu catalyst nanoparticles. Evaluation of the changes in the catalyst nanoparticle coverage and size as a function of implantation parameters reveals that carbon supports functionalized with a combination of nitrogen and fluorine provide the most beneficial interactions, resulting in suppressed particle coarsening and dissolution. Benefits of a carefully tuned support system modified with fluorine and nitrogen surpass those obtained with nitrogen (no fluorine) modification. Ion implantation of iodine into HOPG results in a consistent amount of structural damage to the carbon matrix, regardless of dose. For this modification, improvements in stability are similar to nitrogen modification; however, the benefit is only observed at higher dose conditions. This indicates that a mechanism different than the one associated with nitrogen may be responsible for the improved durability.

Bimodal-sized Pt–Sn and Ru–alloy catalysts for the electro-oxidation of ethanol were synthesized using a novel templating approach and evaluated for ethanol oxidation in alkaline media. This templating approach leads to trimodal-sized catalyst particles embedded in and on bimodal-pore carbon support. Electrochemical evaluation suggested that Pt–Sn phases enhance dehydrogenation and/or C–C bond splitting, while Pt–Ru phases facilitates complete oxidation of the intermediate reaction product CO. The criteria for best-performing catalyst are derived from studies and found to be 2–5 nm Pt(Sn) and the addition of Ru is conjectured to be beneficial. Mass transport effects observed demonstrates that it is possible to effect catalytic performance using the hierarchically structured templating approach used.