In this letter, the feasibility of a 40‐Gb/s subcarrier multiplexed optical transmission system using low‐cost optical electronic components and CMOIS IC technology is studied. A test chip and its measurement results are reported. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 1272–1274, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22433

The feasibility of a 40 Gb/s subcarrier modulated optical transmission system using low-cost optoelectronic components and CMOS IC technology is presented. The optical channel impairments are studied. A complete DSP framework is developed to cancel out the optical channel impairments as well as analog circuit imperfections. To validate that the 40 Gb/s system can be implemented in CMOS, an integrated QAM-16 transceiver with a carrier frequency of 13.32 GHz was designed and fabricated in a 0.14 mum, 1.5 V CMOS technology. The test chip occupies 3.6 mm2 of area and consumes 340 mW of power. Measurement results for a transmission link consisting of the CMOS QAM-16 modulator/demodulator, a directly modulated laser (DML), a 30 km single mode fiber and a p-i-n photo-detector are reported

Incorporating the direct-conversion architecture, a 5-GHz band radio transceiver front end chipset for wireless LAN applications is implemented in a 0.25-/spl mu/m CMOS technology. The 4-mm/sup 2/ 5.25-GHz receiver IC contains a low noise amplifier with 2.5-dB noise figure (NF) and 16-dB power gain, a receive mixer with 12.0 dB single sideband NF, 13.7-dB voltage gain, and -5 dBm input 1-dB compression point. The 2.7-mm/sup 2/ transmitter IC achieves an output 1-dB compression of -2.5 dBm at 5.7 GHz with 33.4-dB (image) sideband rejection by using an integrated quadrature voltage-controlled oscillator. Operating from a 3-V supply, the power consumptions for the receiver and transmitter are 114 and 120 mW, respectively.

As both wireless and optical communications systems move towards high-data-rate applications, high-frequency low-phase-noise oscillators are important building blocks in the receiver and transmitter design. CMOS oscillators with integrated inductors are therefore well suited for such applications. This paper describes two integrated CMOS LC oscillators designed for operation over 10 GHz. The first one is based on the ring-coupled quadrature VCO configuration with wide tuning range, while the other is a 4-stage ring oscillator using inductive load. Fabricated in a 0.25-/spl mu/m CMOS technology, both oscillators can operate from a single supply voltage as low as 1.5 V. The highest operating frequencies for the quadrature VCO and ring oscillator are 11 and 12.55 GHz, respectively.

Phase noise and frequency tuning range are key performance parameters of high-frequency voltage-controlled oscillators (VCOs). To achieve low phase noise, LC sinusoidal oscillators with high quality factor (Q) are preferred to other topologies, such as inverter-based ring oscillators. The frequency tuning of LC oscillators can be readily achieved with varactor diodes either on-chip or external. The frequency tuning range is often limited by low supply voltage and maximum variable capacitance available to varactors at high frequencies when on-chip inductors are used. Other frequency tuning approaches include varying current in the resonator to alter effective capacitance, or varying relative weighting between two different LC resonators. While the former approach varies loop gain in addition to the phase, the latter requires careful choice of the resonators and their Qs for stable oscillations. This VCO architecture incorporates two coupled fixed-frequency LC oscillators to generate a variable-frequency output by varying the coupling between two oscillators.