This book covers the major transimpedance amplifier (TIA) topologies and their circuit implementations for optical receivers. This includes the shunt-feedback TIA, common-base TIA, common-gate TIA, regulated-cascode TIA, distributed-amplifier TIA, nonresistive feedback TIA, current-mode TIA, burst-mode TIA, and analog-receiver TIA. The noise, transimpedance, and other performance parameters of these circuits are analyzed and optimized. Topics of interest include post amplifiers, differential vs. single-ended TIAs, DC input current control, and adaptive transimpedance. The book features real-world examples of TIA circuits for a variety of receivers (direct detection, coherent, burst-mode, etc.) implemented in a broad array of technologies (HBT, BiCMOS, CMOS, etc.).

Chapter EFree Access Adaptive Equalizers Eduard Säckinger, Eduard SäckingerSearch for more papers by this author Book Author(s):Eduard Säckinger, Eduard SäckingerSearch for more papers by this author First published: 22 September 2017 https://doi.org/10.1002/9781119264422.app5 AboutPDFPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShareShare a linkShare onFacebookTwitterLinked InRedditWechat References O. E. Agazzi, M. R. Hueda, D. E. Crivelli, H. S. Carrer, A. Nazemi, G. Luna, F. Ramos, R. López, C. Grace, B. Kobeissy, C. Abidin, M. Kazemi, M. Kargar, C. Marquez, S. Ramprasad, F. Bollo, V. Posse, S. Wang, G. Asmanis, G. Eaton, N. Swenson, T. Lindsay, and P. Voois. A 90 nm CMOS DSP MLSD transceiver with integrated AFE for electronic dispersion compensation of multimode optical fibers at 10 Gb/s. IEEE J. Solid-State Circuits, SC-43(12): 2939– 2957, 2008. H.-M. Bae, J. B. Ashbrook, J. Park, N. R. Shanbhag, A. C. Singer, and S. Chopra. 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A 4-channel 1.25–10.3 Gb/s backplane transceiver macro with 35 dB equalizer and sign-based zero-forcing adaptive control. IEEE J. Solid-State Circuits, SC-44(12): 3547– 3559, 2009. Analysis and Design of Transimpedance Amplifiers for Optical Receivers ReferencesRelatedInformation

The optimum sizing of the front-end FET in transimpedance amplifiers (TIA) is revisited. Analytical solutions based on a second-order shunt-feedback TIA model that includes the feedback-resistor noise are derived. It is shown that the optimum FET size can be smaller or larger than suggested by the well-known capacitive matching rule, depending on whether the noise optimization is carried out under a constant gain-bandwidth-product constraint or a constant load-capacitance constraint.

The excess noise factor , also known as Ogawa’s noise factor, is frequently used in the literature on optical receivers to calculate the noise and sensitivity of FET front-ends. After revisiting its definition and clarifying its applications and limitations, we derive an analytical expression for in terms of the channel noise factor , the gate noise factor , and the correlation coefficient . We explain the difference between and and discuss the dependence of on the source (photodetector) capacitance. The latter dependence, which is weaker than previously thought, is verified by circuit simulations. Additional insight is obtained by complementing van der Ziel’s noise model with Pospieszalski’s noise model. Finally, we use the derived expression for to calculate its value from measured noise data of a 0.18m CMOS technology.

The transimpedance limit describes the maximum transimpedance that a transimpedance amplifier (TIA) can attain for a given bandwidth and technology. We analyze and compare this limit for a wide variety of TIA topologies thus exposing their relative merits. The topologies considered are the shunt-feedback TIA with single and multistage amplifier, the shunt-feedback TIA with feedback capacitor, the shunt-feedback TIA followed by a post amplifier, the shunt-feedback TIA with a current amplifier, the common-base/gate feedforward TIA, the shunt-feedback TIA with a common-base/gate input stage, and the shunt-feedback TIA with a regulated-cascode input stage. The analysis includes a discussion of the conditions under which the limit is realizable.

In this letter, the feasibility of a 40‐Gb/s subcarrier multiplexed optical transmission system using low‐cost optical electronic components and CMOIS IC technology is studied. A test chip and its measurement results are reported. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 1272–1274, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22433

The feasibility of a 40 Gb/s subcarrier modulated optical transmission system using low-cost optoelectronic components and CMOS IC technology is presented. The optical channel impairments are studied. A complete DSP framework is developed to cancel out the optical channel impairments as well as analog circuit imperfections. To validate that the 40 Gb/s system can be implemented in CMOS, an integrated QAM-16 transceiver with a carrier frequency of 13.32 GHz was designed and fabricated in a 0.14 mum, 1.5 V CMOS technology. The test chip occupies 3.6 mm2 of area and consumes 340 mW of power. Measurement results for a transmission link consisting of the CMOS QAM-16 modulator/demodulator, a directly modulated laser (DML), a 30 km single mode fiber and a p-i-n photo-detector are reported

An active POTS filter consisting of a small external L-C low-pass filter and a selectivity booster chip is presented. The filter achieves an ADSL attenuation of more than 70 dB at 30 kHz while maintaining a passband flatness of 0.2 dB. This active filter requires fewer transformers and is smaller than a passive filter with the same performance. The 0.5-mu m CMOS booster chip contains a fifth-order continuous-time filter, a low output-impedance driver, and an active rectifier and consumes 50 mW from a 5-V AC supply.

This paper reports experiments measuring the effects of finite precision arithmetic in the range of 4 to 16 bits on three particular pattern-recognition algorithms: an optical character recognizer [1], a pen-based character recognizer [2], and a speech recognizer [3]. The measurements shows that large portions of these algorithms can be implemented with 8-bit arithmetic (e.g. using Intel's MMXTM instruction set) while incurring only a negligible loss in recognition accuracy.

Free Access Appendix H: Acronyms Eduard S채ckinger, Eduard S채ckingerSearch for more papers by this author Book Author(s):Eduard S채ckinger, Eduard S채ckingerSearch for more papers by this author First published: 27 January 2005 https://doi.org/10.1002/0471726400.app8 AboutPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinked InRedditWechat Broadband Circuits for Optical Fiber Communication RelatedInformation

This programmable DSP is the first implementation of the scaleable-bus-based platform, Daytona for communication infrastructure equipment and broadband access terminals. An aggressive memory hierarchy minimizes bus traffic and meets the performance requirements for large multi-channel signal processing applications with the smallest possible memory footprint. The chip was implemented with full custom memories with 0.35 /spl mu/m features and the remaining logic is implemented with standard cells. The 207 mm/sup 2/ 0.25 /spl mu/m CMOS chip achieves 100 MHz and dissipates 4 W at 3.3 V.

An optical receiver front-end for SONET OC-48 (2.5 Gb/s) is shown. The limiting amplifier (LA) receives a small-non-return to zero (NRZ) voltage signal (e.g., 8 mV/sub pp/) from the transimpedance amplifier (TIA) and amplifies it to a level (e.g. 250 mV/sub pp/) sufficient for the reliable operation of the clock and data recovery circuit. The noise contribution of the LA must be small compared to that of the TIA so that the overall bit error rate and sensitivity are not affected adversely. Currently, commercial 2.5 Gb/s SONET systems are composed of several discrete chips implemented in GaAs and more recently silicon bipolar technology. The future trend, however, is to integrate most of the front-end together with the digital framer on a single CMOS chip. Furthermore, the integration of multiple 2.5 Gb/s channels on a single CMOS chip is desirable for wavelength division multiplexing (WDM) application. CMOS amplifiers for optical receivers and related applications with bandwidths up to 2.1 GHz are recently reported. This CMOS limiting amplifier with improved bandwidth (3 GHz) and noise figure (16 dB) is suitable for 2.5 Gb/s SONET receivers. Power dissipation is 53 mW and the chip is fabricated in a standard 2.5 V, 0.25 /spl mu/m CMOS technology. This result is achieved with: (i) Inverse scaling to increase gain-bandwidth and reduce power dissipation while keeping noise and offset voltage low and (ii) active inductors to increase gain-bandwidth and improve gain stability. The active area of the amplifier is 0.03 mm/sup 2/, less than 10% that of a comparable design with spiral inductors.