One-dimensional analytical model suitable for large scale cells under illumination has been developed. The model is based on two main assumptions. The first one is that in the case of wide gap semiconductors the concentration of the free dark carriers related to the non-equilibrium (generated) carriers can be neglected. This assumption simplifies the transport equations. In the second one, we assume an mean value (E-gc) of the electrical field across the i-layer in accordance with the relationship (E(gc)w = integral(w)(0)E(gx)dx) were E-gx is the field created by light generated charges, w is the thickness of the i-layer of the cell. These assumptions allow us to transform the system from continuity and transport equations in a first order differential equation that simplify the solution of the system. The experimental solar cell characteristics are fitted using the finite number of fundamental parameters, namely the electron and hole diffusion lengths (I-n ands I-p, respectively), the light intensity (L-0) and light absorption coefficient (alpha). If we know the values of L-0 and alpha, we can derive from the fitted curve the I-p, value with satisfactory accuracy. The value of I-n influences more weakly on the I-V dependence. A simple formula for optimal thickness of the i-layer of the cell is derived.

Being of interest for plastic electronics, ion-beam produced nanostructure, namely silicon ion (Si+) implanted polymethyl-methacrylate (PMMA) with ultrathin nanostructured dielectric (NSD) top layer and nanocomposite (NC) buried layer, is examined by electric measurements. In the proposed field-effect organic nanomaterial structure produced within the PMMA network by ion implantation with low energy (50 keV) Si+ at the fluence of 3.2 x 10(16) cm(-2), the gate NSD is ion-nanotracks-modified low-conductive surface layer, and the channel NC consists of carbon nanoclusters. In the studied ion-modified PMMA field-effect configuration, the gate NSD and the buried NC are formed as planar layers both with a thickness of about 80 nm. The NC channel of nano-clustered amorphous carbon (that is an organic semiconductor) provides a huge increase in the electrical conduction of the material in the subsurface region, but also modulates the electric field distribution in the drift region. The field effect via the gate NSD is analyzed. The most important performance parameters, such as the charge carrier field-effect mobility and amplification of this particular type of PMMA-based transconductance device with NC n-type channel and gate NSD top layer, are determined.

Epitaxial GaN film formation on bare 6H-SiC(0001) substrates via the process of transformation of Ga droplets into a thin GaN film by applying hyperthermal nitrogen ions is investigated. Pre-deposited Ga atoms in well defined amounts form large droplets on the substrate surface which are subsequently nitridated at a substrate temperature of 630 °C by a low-energy nitrogen ion beam from a constricted glow-discharge ion source. The Ga deposition and ion-beam nitridation process steps are monitored in situ by reflection high-energy electron diffraction. Ex situ characterization by x-ray diffraction and reflectivity techniques, Rutherford backscattering spectrometry, and electron microscopy shows that the thickness of the resulting GaN films depends on the various amounts of pre-deposited gallium. The films are epitaxial to the substrate, exhibit a mosaic like, smooth surface topography and consist of coalesced large domains of low defect density. Possible transport mechanisms of reactive nitrogen species during hyperthermal nitridation are discussed and the formation of GaN films by an ion-beam assisted process is explained.

The electrical properties of polymethylmethacrylate (PMMA) after implantation with silicon ions accelerated to an energy of 50 keV are studied under DC electric bias field. The electrical response of the formed material is examined as a function of Si+ fluence in the range 1014 − 1017 cm−2. The carbonaceous subsurface region of the Si+-implanted PMMA displays a significant DC conductivity and a sizable field effect that can be used for electronic applications.

We report on a field-effect transistor-like memory element based on chargeable organic dielectric as gate in polymethylmethacrylate (PMMA) implanted with Si+ ions (50 keV energy, dose 10(16) ions/cm(2)). Utilizing the carbonized nanostructured active material with thickness of about 100 nm, as well as the organic interface created by silicon ion implantation in the subsurface region of the host polymer, the proposed memory cell exhibits electrical retention properties upon applying a gate voltage. The observed memory function is attributed to both the charged gate dielectric and organic interface formed in Si+-implanted PMMA. The ON and OFF-states can be written to the device by applying appropriate voltages to the gate electrode. Key feature of the memory element is the low writing voltage.

The electrical conductivity and field-effect transconductance of polymethylmethacrylate (PMMA) subjected to implantation with 50keV silicon ions at doses in the range from 1014 to 1017 ions/cm2 were examined. The electrical response of Si+-implanted PMMA was studied by direct current (DC) and alternating current (AC) measurements and was related to the structure formed in the host polymer. In addition to the sizable enhancement of the conductivity with the implantation dose, the field-effect transconductance found in Si+-implanted PMMA shows the potential of this material for soft-electronic applications.

The influence of high energy electron (23 MeV) irradiation on the electrical characteristics of p-channel polysilicon thin film transistors (PSTFTs) was studied. The channel 220 nm thick LPCVD (low pressure chemical vapor deposition) deposited polysilicon layer was phosphorus doped by ion implantation. A 45 nm thick, thermally grown, SiO2 layer served as gate dielectric. A self-alignment technology for boron doping of the source and drain regions was used. 200 nm thick polysilicon film was deposited as a gate electrode. The obtained p-channel PSTFTs were irradiated with different high energy electron doses. Leakage currents through the gate oxide and transfer characteristics of the transistors were measured. A software model describing the field enhancement and the non-uniform current distribution at textured polysilicon/oxide interface was developed. In order to assess the irradiation-stimulated changes of gate oxide parameters the gate oxide tunneling conduction and transistor characteristics were studied. At MeV dose of 6×1013 el/cm2, a negligible degradation of the transistor properties was found. A significant deterioration of the electrical properties of PSTFTs at MeV irradiation dose of 3×1014 el/cm2 was observed.

The transient conductivity and polarization of nano-sized ZrO2 thin films were investigated. RF magnetron sputtering was used for the deposition of the films with different thicknesses on poly-Si. The layers were annealed at 600 and 850 degrees C in oxygen ambient. Capacitors fabricated with top Al contacts were studied by current-voltage and hysteresis loop measurements. The dependence of the polarization on thickness and annealing temperature was evaluated.

Leakage currents through Al/ZrO2/SiO2/n-Si metal-insulator-semiconductor (MIS) capacitors were studied. Thin SiO2 films were chemically grown on monocrystalline phosphorous doped silicon wafers. Zirconia films with thicknesses of 15 and 50 nm were deposited by radio frequency (rf) magnetron sputtering and, then, annealed in oxygen ambient at 850 ○C, for 1 h. The dielectric constant of the sputtered and annealed ZrO2 layer was of about 17.8. The equivalent oxide thickness (EOT) of the stack 15 nm and 50 nm-ZrO2/SiO2 structure was estimated to be 3.2 nm and 10.7 nm, respectively. The temperature dependence of the leakage currents was explained by Poole-Frenkel (PF) conduction mechanism. Shallow trap levels in the studied structure of about 0.2 eV and 0.46 eV were calculated. The existence of A and D-defects, due to the sputtering and high temperature annealing in oxygen, was suggested.

The influence of MeV electrons irradiation on the gate oxide layers of hydrogenated polysilicon thin film transistors (TFTs) was investigated by measuring gate leakage currents and threshold voltages. The experimental data revealed a decrease of oxide trap density and increase of positive oxide charge. Improvement in the interface roughness and in the oxide quality near the bottom interface was observed.

A rapid thermal annealing (RTA) treatment was used to improve the performance of ammonia sensors based on a MOSFET structure with a thin SnO2 layer used as a gate. RTA processes in vacuum with duration of 15–60 s and temperatures 600–800°C were applied. After thermal treatment samples are subjected to a cycle of successive steps with different environmental conditions in order to reveal the sensitivity, selectivity and reversibility of the response. It is found that the RTA process at 800°C, with duration of 60 s, rise time of 2 s and fall time of 4 s results in enhanced sensitivity to the active agent (NH3), reduced cross-sensitivity to water vapours (relative humidity) and improved reversibility of the device's response. This overall improvement of the performance is explained by surface changes of the SnO2 layer, provoked by the RTA process. Such changes are revealed by reflection high-energy electron diffraction (RHEED) and scanning electron microscopy (SEM).

The time-to-breakdown (tbd) of polysilicon/polyoxide/polysilicon structures, hydrogenated by hydrogen ion implantation, is investigated. The ln(tbd) versus 1/Eox projection lines are corrected by using an average oxide field enhancement factor for the interface polysilicon/thermally grown polyoxide. A field acceleration factor G≈270 MV/cm in the time-to-breakdown projection line is obtained. The obtained lower values of the field acceleration factor G, in comparison to as-grown polyoxides, are explained in the terms of the oxide traps generated during the hydrogen ion implantation.

Fowler–Nordheim tunneling currents in hydrogen ion implanted and as-grown SiO2 films, thermally grown on polycrystalline silicon(polysilicon), have been investigated. The ion implantation is performed through the SiO2 films for hydrogenation of the grain boundary states in the polysilicon layer on which the SiO2 is grown. A model of Groeseneken and Maes is used to include in the calculations the field enhancement caused by asperities at the SiO2–polysilicon interface. The oxide field reduction, caused by electron capture in initially neutral electron traps into the SiO2, is also modeled. Electron trapping probabilities, defined as the product of the bulk electron trap density in SiO2 and the electron capture cross section of the traps are determined in both as-grown and hydrogen ion implanted oxides. In the hydrogen ion implanted oxides electron trapping probabilities higher than three orders of magnitude are obtained. Native electron traps in the as-grown oxides with capture cross section of the order of 10−20cm2, as well as ion implantation generated electron traps with capture cross section of the order of 10−18cm2 are deduced from the calculated trapping probabilities.

Current response of a MOSFET humidity gas sensors is investigated, depending on the voltage applied (constant or pulsed) in a temperature interval of 10–50°C. A model, based on the variation Δϕ of the p–n junction potential barrier, is used for the explanation of the results. Δϕ is found to be strongly dependent on the mode of operation, on the pause/pulse duration and on the temperature in the range of relative humidity 10–90%.

Time-to-breakdown (tbd) of polysilicon/polyoxide/polysilicon structures is investigated on small and large area capacitors. The ln(tbd) versus 1/Eox projection lines are corrected by using an average oxide field enhancement factor for the interface polysilicon/thermally grown polyoxide. A field acceleration factor G≈320MV/cm in the time-to-breakdown projection line is obtained. It is shown that the fast prediction of time-to-breakdown can be achieved with short stress time measurements in structures of different area.

The relationship between low-frequency drain current noise spectral density SI and grain-boundary potential barrier height Vb is investigated in high-temperature-processed polycrystalline silicon thin-film transistors. It is demonstrated that a general empirical relationship exists between SI and Vb indicating that the noise sources are located at the grain boundaries. The implications of the obtained relationship between SI and Vb from the practical viewpoint are discussed.

Leakage current evolution during two different modes of electrical stressing in hydrogenated-undoped n-channel polysilicon thin film transistors (TFTs) is studied in this work. On-state bias stress (high drain bias and positive gate bias) and off-state bias stress (high drain bias and negative gate bias) were performed in order to study the degradation of the leakage current. It is found that during off-state bias stress the gate oxide is more severely damaged than the SiO2-polySi interface. In contrast, during on-state bias stress, two different degradation mechanisms were detected which are analyzed.

Polycrystalline silicon thin-film transistor (polysilicon TFT's) characteristics are evaluated by using a low-frequency noise technique. The drain current fluctuation caused by trapping and detrapping processes at the grain boundary traps is measured as the current spectral density. Therefore, the properties of the grain boundary traps can be directly evaluated by this technique. The experimental data show a transition from 1/f behavior to a Lorentzian noise. The 1/f noise is explained with an existing model developed for monocrystalline silicon based on fluctuations of the inversion charge near the silicon-oxide interface. The Lorentzian spectrum is explained by fluctuations of the grain boundary interface charge with a model based on a Gaussian distribution of the potential barriers over the grain boundary plane. Quantitative analysis of the 1/f noise and the Lorentzian noise yield the oxide trap density and the energy distribution of the grain boundary traps within the forbidden gap.

A study on hot-carrier phenomena in high temperature processed undoped and hydrogenated n-channel polysilicon thin film transistors (TFTs) is presented. First, stress conditions are determined by photon emission measurements during impact ionization condition. Next four stress regimes are performed. We distinguish two modes of stress conditions according to drain voltage during stressing: High drain voltage stress (HDVS) and low drain voltage stress (LDVS). Each of these modes gives different results when applied to our TFTs. During HDVS condition, two regimes are observed. First, hot-hole injection into the oxide occurs synchronically with interface-state generation. At a second stage, this mechanism saturates and electron injection through the polySi–SiO2 barrier takes place with less interface states generated. In contrast, during LDVS conditions no saturation of interface-state generation is observed and two regimes of transconductance degradation appear. The distribution in the gap of the stress-induced interface states is calculated by a known method. Finally, on- and off-state current stress was studied. Off-stressing affects mainly the gate oxide and is not accompanied by measurable impact ionization phenomena and thus no considerable interface-state generation.

The photon emission induced by the drain avalanche in polycrystalline silicon thin-film transistors (polysilicon TFTs) has been studied in wide drain and gate voltage ranges. As the photon emission phenomenon is closely related to hot-carrier effects, the gate and drain bias conditions for maximum device degradation have been determined from measurements of the emitted light intensity. In n-channel polysilicon TFTs, the effects of bias stressing at the maximum light emission are related to hot-hole trapping into the gate oxide near the drain and to formation of acceptor-like interface states consisted of midgap states and band tails.