We extend an analytical electrical compact model, originally developed for planar InGaN/GaN quantum-well (QW) micro-light-emitting diodes (mu LEDs), to core-shell InGaN/GaN QW nanowire-array mu LEDs. By exploiting the near invariance of the measured current density-voltage (J-V) characteristics with respect to the number of nanowires, the array can be represented by an equivalent single-nanowire model, enabling extraction of average electrical parameters, including the effective hole diffusion coefficient, as well as the series and thermal resistances. The model enables determination of the hole density injected into the QW and direct extraction of the radiative recombination coefficient B from the dependence of optical power on hole density without requiring specialized measurements. Incorporation of the measured light extraction efficiency and the hole density into the ABC framework allows prediction of the external quantum efficiency (EQE) as a function of both current density and hole concentration. A hole concentration-dependent Auger coefficient is introduced to account for phase-space filling effects at high injection levels, reproducing the observed EQE asymmetry not described by the conventional ABC model. The extracted radiative recombination coefficient further enables evaluation of the modulation bandwidth, which is relevant for visible-light communication applications.

This work presents a physics-based compact model for double-gate junctionless field-effect transistors, with emphasis on accurately capturing the impact of ungated source/drain extensions on the drain current characteristics. The model is validated against two-dimensional device simulations performed using Silvaco ATLAS for two channel doping concentrations and a wide range of ungated extension lengths. To isolate the contribution of the access regions and clarify the effective channel length, all mobility degradation models were disabled in the simulations, allowing the observed current degradation to be attributed solely to the series resistance of the ungated extensions. The proposed formulation includes an analytical factor ξ that accounts for the reduced electrostatic influence of the source and drain terminals on the channel potential, as well as a closed-form expression for the fringe capacitance associated with the ungated regions. The resulting drain current model demonstrates very good agreement with numerical simulations across different geometries and doping levels. Model symmetry is further verified through a Gummel symmetry test, confirming the physical consistency of the formulation. Owing to its analytical nature and physical transparency, the proposed model is well suited to serve as a core building block for higher-level compact models of JL devices.

In this study, we investigate the impact of the source and drain (S/D) underlap regions on the electrical characteristics of short-channel double-gate junctionless transistors (DG JLTs). Analytical expression for the potential distribution in the gate overlap and S/D underlap regions is introduced, which relies on a single fitting parameter and the gate fringe capacitance in the underlap regions. The derived potential distribution shows good agreement with simulation results across different underlap lengths and gate/drain bias voltages. Consequently, new expressions for the threshold voltage and the subthreshold swing coefficient of DG JLTs are developed comprising the effect of the S/D underlap regions, which are used for upgrading our previous continuous and symmetric analytical drain current compact model. The findings highlight the significant influence of the S/D underlap regions on the electrical characteristics of DG JLTs, suggesting a need for their careful consideration in drain current compact modeling.

We present a simplified model for the hole injection recombination current in multiple quantum-well (MQW) micro-light-emitting diodes (mu LEDs) by representing the MQWs as a single equivalent quantum well (EQW). Building on our initial model, we have reformulated the fundamental equations, which were previously expressed using the complex analytical Lambert W-0(x) function, in terms of applied forward voltage, material properties, and model parameters. The resulting model provides a simplified and concise expression for the hole injection recombination current, applicable within the forward operating region. It incorporates key factors such as the EQW position within the depletion region, the hole diffusion coefficient, the electrical series resistance, and the thermal resistance. This refined model forms the foundation for an explicit methodology to extract both the injection recombination current parameters and the thermal resistance of the mu LED. Furthermore, we introduce an empirical analytical compact model for optical power density, which is linked to the injection recombination current density (J) as a power function of the Lambert W0(J) function, applicable across all injection recombination current regimes. We have also developed a methodology to extract the three relevant optical parameters involved. The proposed analytical electro-optical compact model, validated against experimental data from green and blue mu LEDs, is well suited for the electrical and optical simulation of quantum-well-based mu LEDs. (c) 2025 Society of Photo-Optical Instrumentation Engineers (SPIE)

This paper presents a novel physics-based analytical model for the injection recombination current in micro-light emitting diodes (μLEDs) with multiple quantum wells (MQWs), specifically excluding trap-assisted tunneling contributions at low forward voltages. The model simplifies the complex MQW structure by representing MQWs as a single equivalent quantum well (EQW). The μLED current is attributed to the recombination of injected holes and electrons within this EQW. Key parameters of the model encompass the EQW’s position within the depletion region, hole diffusion coefficient, series resistance, and thermal resistance of the device. Experimental validation of the model is performed using current–voltage characteristics obtained from InGaN/GaN QW μLEDs.

The threshold voltage of rectangular p-type triple-gate junctionless transistors (JLTs) is studied experimentally using the transconductance derivative (dg m /dV g ) method, after correcting the drain current from the impact of series resistance.The effect of series resistance on the dg m /dV g behavior is highlighted.In the investigated devices, the high series resistance affects the dg m /dV g behavior more than the short-channel effects.The results show that, in addition to the flat-band voltage, for the first time two threshold voltages V th1 and V th2 are observed within the partial depletion region in devices with channel length varying from 95 to 25 nm.Numerical simulations of the holes density distribution reveal the absence of corner effects due to the unique bulk neutral conduction, whereas V th1 and V th2 correspond to the threshold voltages of the side gates and top gate, respectively.The correct extraction of the flat-band voltage has been confirmed with numerical simulations of the holes density distribution.Experimental measurements of p-type JLTs with variable being the fin width indicate that the threshold voltages V th1 and V th2 are due to the different interface states density at the side and top gates.

The low-frequency noise of short channel triple-gate junctionless (TG JL) MOSFET has been investigated in the frequency and time domains before and after hot carrier aging (HCA). The objective of this work is to investigate the interaction between HCA/flicker noise (1/f noise) and random telegraph noise (RTN) of short channel length device (L = 25 nm) exhibiting high density of interface traps. Significant variation in the noise spectral density has been observed between the fresh and the stressed device, related to the occurrence of generation-recombination (g-r) noise. Gate voltage dependence of g-r noise has been observed, assigned to gate dielectric traps and interface traps. In the fresh device, the noise is dominated by 1/f noise and multiple level RTN due to interface traps. In the stressed device, the 1/f noise is overlaid by multiple level RTN due to traps in the gate dielectric and at the gate insulator-silicon interface. The multiple level RTN relative amplitude can be described by the generic carrier number with correlated mobility fluctuations model as for the two level RTN detected in long channel devices (L = 65 and 95 nm).

In this work, a continuous and symmetric trans-capacitance compact model for triple-gate junctionless MOSFETs is presented, valid in all regions of operation. Initially, the expressions of the gate, drain and source total charges are analytically derived based on a continuous and symmetric drain current compact model already developed. Then, the intrinsic capacitances are calculated via the differentiation of the terminal charges, verified against TCAD simulation data. The AC symmetry tests of the trans-capacitance compact model are thoroughly investigated.

In this article, we investigate the impact of the hot carrier (HC) aging on the performance of nanoscale n-channel triple-gate junctionless MOSFETs with channel length varying from 95 down to 25 nm. The devices were electrically stressed in the ON-state region of operation at fixed gate voltage ${V}_{g} = {1.8}$ V and drain bias ${V}_{d} = {1.8}$ V, with the stress time being a variable parameter. The device degradation was monitored through the relative change with stress time of the threshold voltage, subthreshold swing, linear drain current, low-field mobility, series resistance, and gate current. For relatively long-channel transistors ( ${L} = {95}$ nm), the threshold voltage and the subthreshold swing remain almost unchanged, whereas the ON-state drain current is degraded showing a good correlation with the series resistance degradation, caused by HC-induced damage in the drain region. For short-channel transistor ( ${L} = {45}$ nm), the HC-induced damage is extended in the channel region: interface traps are generated, exhibiting good correlation with both threshold voltage and low-field mobility degradations. For the very short-channel device ( ${L} = {25}$ nm), after long stress time, the HC-induced interface degradation is severe, causing a continuous increase of the ideality factor with increasing the gate voltage.

This paper investigates the local variability in nanoscale triple-gate junctionless FinFETs utilizing an analytical symmetric and continuous compact model combined with Monte Carlo simulations. Initially, the device parameters are extracted from the experimental transfer characteristics, such as threshold voltage, ideality factor, low-field mobility, source-drain series resistance, channel length modulation factor and mobility degradation factor. Then, statistical analysis is performed to calculate the mean values and standard deviations of the differences of the aforementioned parameters for the local pairs and large number of devices with reference to the mean value of all dies. Monte Carlo simulations allow the compact model to reproduce successfully the drain current local variability. Most important process parameters have been considered and assessed as variability sources, by using the error propagation formula and exploiting the proposed drain current compact model. Successful application to experimental data, revealed the extent of the variabilities in most important process parameters of the devices (sources of variability).

In this brief, we upgrade our initial drain current compact model for triple-gate junctionless transistors (JLTs) to a continuous model satisfying the source/drain (S/D) symmetry. This is achieved by reformulating the key equations of our original model, using Lambert-function-based terminal charges. The upgraded model is compact, bulk-referenced valid in all regions of operation and it is validated through comparison with experimental data to verify its accuracy. The symmetry condition is investigated and validated performing the dc Gummel symmetry test (GST) for all derivatives up to the fifth order.

In this work, we extend our analytical compact model for nanoscale junctionless triple-gate (JL TG) MOSFETs, capturing carrier transport from drift-diffusion to quasi-ballistic regime. This is based on a simple formulation of the low-field mobility extracted from experimental data using the Y-function method, taking into account the ballistic carrier motion and an increased carrier scattering in process-induced defects near the source/drain regions. The case of a Schottky junction in non-ideal ohmic contact at the drain side was also taken into account by modifying the threshold voltage and ideality factor of the JL transistor. The model is validated with experimental data for n-channel JL TG MOSFETs with channel length varying from 95 down to 25 nm. It can be easily implemented as a compact model for use in Spice circuit simulators.

The low-frequency noise in triple-gate junctionless n-MOSFETs, with channel lengths varying from 95 to 25 nm and operating in the bulk and accumulation modes, is investigated by measurements in the frequency and time domains. The experimental drain current noise spectra present 1/f and Lorentzian-type behavior components. The noise spectra in the time domain reveal that the Lorentzian-type behavior components are due to the capture and emission processes of carriers at discrete gate insulator traps, resulting in random telegraph noise (RTN). The 1/f behavior can be described by the carrier number with the correlated mobility fluctuations model. In the below-threshold region, the conducting channel is isolated from the interface by depletion region. In the above-threshold region (bulk conduction mode), the histograms of the time-domain data show multilevel switching events, from which one or more individual traps can be distinguished. The extracted time constants of two-level RTN signals indicate the interaction of a single trap either with the channel or with both channel and gate. The relative RTN amplitude is described with the carrier number with the mobility correlated fluctuations physics-based model or with the “hole in the inversion layer” stochastic simulation-based model, enabling estimation of the flat-band voltage fluctuation caused by the RTN.

The device transport parameters (subthreshold slope, low-field mobility, series resistance, and threshold voltage) of n-channel triple-gate junctionless transistors are investigated in the temperature range 298-398 K. The temperature dependence of these parameters is analyzed to clarify the mechanisms responsible for the impact of temperature on the device performance. Based on analytical empirical expressions capturing their temperature dependence, our analytical compact model can predict the transfer and output characteristics at elevated temperatures with good accuracy.

A detailed statistical characterization and modeling of drain current local and global variability in 14nm Si bulk FinFET devices is performed. To this end, an analytical mismatch model covering weak to strong inversion region is used to extract the main matching parameters. Our results show that, despite their very aggressive dimensions in terms of Fin width and height, such devices exhibit excellent local and global variability performance. Moreover, a Lambert-W function-based MOSFET compact model is used for MC simulation of local variability.

A complete static and low frequency noise characterization of ultra-thin body InAs MOSFETs is presented. Characterization techniques established for Si MOSFETs are applied in order to extract the electrical parameters and study the behavior of these research grade devices.

A detailed statistical characterization of the drain current low-frequency noise (LFN) in sub-15 nm Si/SiGe Trigate NW pMOSFETs is presented. The slow oxide trap density and distribution, as well as the correlated mobility fluctuations effect are probed for several channel geometries. The LFN variability scaling is also presented and compared to established nano-scale planar CMOS technologies. Our results indicate that such devices demonstrate relatively good gate oxide interface quality and LFN variability levels, despite their very aggressive dimensions and not yet optimized fabrication process.

In this paper, the experimental off-state drain leakage current behavior is systematically explored in nand p-channel junctionless nanowire transistors with HfSiON/TiN/p(+)-polysilicon gate stack. The analysis of the drain leakage current is based on experimental data of the gate leakage current. It has been shown that the off-state drain leakage current in n-channel devices is negligible, whereas in p-channel devices it is significant and dramatically increases with drain voltage. The overall results indicate that the off-state drain leakage current in p-channel devices is mainly due to trap-assisted Fowler-Nordheim tunneling of electrons through the gate oxide of electrons from the metal gate to the silicon layer near the drain region. (C) 2017 Elsevier Ltd. All rights reserved.