A 63nm Twin Flash memory cell with a size of 0.0225 mum2 / 2 (4) bits is presented. The cell is proposed for data Flash products with 4 to 16 Gbit densities. To achieve small cell areas, a buried bit line and an aggressive gate length of ~100 nm are the key features of this 63nm Twin Flash cell. The cell is well capable of 2 and 4 bit operation.
ludovic lattard合作论文数1eike ruttkowski合作论文数1stefano parascandola合作论文数1veronika polei合作论文数1norbert schulze合作论文数1joachim deppe合作论文数1m isler合作论文数1Christoph Ludwig合作论文数1dirk manger合作论文数1boaz eitan合作论文数1e g stein v kamienski合作论文数1michael markert合作论文数1d caspary合作论文数1Stephan Riedel合作论文数1Bach, L.合作论文数1Shur, Y.合作论文数1
Thomas Mikolajick合作论文数Center for Advancing Electronics Dresden, Dresden University of Technology1
David E. Pritchard合作论文数Department of Physics, Massachusetts Institute of Technology1F. Heinrichsdorff合作论文数1Dominik Olligs合作论文数1Ricardo P. Mikalo合作论文数1
Nicolas Nagel合作论文数1Hocine Boubekeur合作论文数1
Assaf Shappir合作论文数Research Institute for Nano-Science and Nano-Technology, Tel Aviv University1
Eli Lusky合作论文数Saifun Semiconductors Ltd.1
