This letter investigates a new select device disturb phenomenon in TANOS NAND flash memories. Since NAND string select devices contain the same charge trap (CT) stack as the memory cells, they are, in principle, programmable. We observe a select threshold voltage increase during cycling of the cell array. This disturb is caused by electron injection from the outermost wordline into the CT layer of the select devices under the erase condition. The increasing select threshold voltage leads to a reduced string current and, finally, to read fails of the NAND string. The mechanism is evaluated by means of electrical measurements and field simulations. Several options to overcome this issue are proposed.

This paper presents charge trapping (CT) cells integrated with a sacrificial liner at the word line (WL) side wall which improves significantly the erase and retention characteristics, currently the main issues in CT memory devices.

TANOS-NAND flash process integration generates various technological difficulties; one of the most relevant is the patterning of TaN metal gates together with Al2O3 high-k dielectrics. BCl3/N2 based high-temperature plasma etching preferably used for structuring high-k materials reveals severe etch damage effects at the TaN sidewalls. Plasma treatments with different etch gases (BCl3/N2; O2/Ar; Cl2/Ar) were used for detailed analyses of chemical effects on the TaN layer. The damage induced by BCl3/N2 based plasma was investigated and characterized using blanket wafers. Approaches to overcome this obstacle are proposed.

This article demonstrates that the scaling of the charge trap layer leads to an increasing charge loss in retention mode. This result is assigned to the fact that the blocking aluminum oxide is the main leakage path. It is further presented that the charge distribution moves towards the top oxide during programming and therefore shortens the distance to the leakage path. For thinner charge trap layers, the traps close to the aluminum oxide interface are already filled at lower DeltaVt resulting in higher retention loss for the same Vt shift.

This publication investigates the program simulation of charge trapping memory devices in detail. Three different aspects of the simulation are highlighted which have a major impact on the program characteristics in trap based memories. The analysis is done by a comparison between measurement and simulation. It is shown that the trap capture cross section, the bottom oxide to storage nitride energy band offset and the tunneling injection point, under modified Fowler-Nordheim tunneling conditions, are of major importance for highly accurate simulations. The results provide deeper insight into the mechanisms dominating the program behavior in charge trapping memory devices.

This article details an anomalous erase behavior in charge trapping memory devices which is visible in a characteristic erase hump in transient erase curves. For an initial period of time a Vt increase is seen when erase condition are applied to virgin cells before the expected erasing takes place for longer erase pulse duration. This is attributed to charges injected from the gate corners to the areas above source and drain. This effect significantly deteriorates the erase performance of charge trapping devices compared to the intrinsic erase behavior which can be measured at large area capacitor structures.

Floating gate NAND flash memory arrays with 64 cells per string and high-k inter poly dielectric have been fabricated on a 36 nm ground rule using sub-lithographic patterning techniques (pitch fragmentation). The influence of pitch fragmentation inherent critical dimension variations on the electrical parameters of the memory cells such as string saturation current, initial threshold voltage, and program/erase performance has been investigated in detail.

A 63nm Twin Flash memory cell with a size of 0.0225 mum2 / 2 (4) bits is presented. The cell is proposed for data Flash products with 4 to 16 Gbit densities. To achieve small cell areas, a buried bit line and an aggressive gate length of ~100 nm are the key features of this 63nm Twin Flash cell. The cell is well capable of 2 and 4 bit operation.

A 90nm Twin Flash memory cell with a size of 0.029/spl mu/m/sup 2//bit (3.5F/sup 2/) is presented. This cell is introduced first in a 1.8V, 2Gbit data flash. The Twin Flash technology is based on a shallow trench isolation (STI) bounded cell with local interconnect (LI) and serves for both advanced code and data flash storage memories. Beyond the 90nm node the scalability of the Twin Flash device is shown for 70 and 60nm node. The 90nm technology and its scaling follow the DRAM scaling path.