Suppression of surface donors (SDs) in AlGaN/GaN MOS-HEMTs represents a promising approach towards realization of normally-off switching devices with high threshold voltage. In this work, density of oxide/barrier interface traps (D it ) was determined in AlGaN/GaN MOS-HEMT structures with different SDs density (Nds), resulted from HCl pre-treatment variation. The results suggest deteriorated interface quality for sample without HCl cleaning. D it was found to increase from ~10 12 to ~10 13 eV -1 cm -2 in the energy range of 0.8 to 1.1 eV below the conduction band edge for structures with and without HCl cleaning step, respectively. On the other hand, our analysis indicates negligible contribution of interface traps to observed threshold voltage in thermal equilibrium. This indicates the nature of SDs to be different from that of interface traps.

AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors (MOS-HEMTs) represent an important technology for future high-efficient power and RF electronics. Due to oxide/semiconductor interface issues, fabrication of reliable MOS gate stack is still challenging, however. In this work we investigated the influence of gate oxide preparation technique to static and pulsed-mode operation of Al 2 O 3 /GaN/AlGaN/GaN MOS-HEMTs. Devices with gate oxide prepared by high-temperature MOCVD and low-temperature ALD using water vapour or ozone as oxidants are compared in terms of dynamic on-state resistance (R DSon ), threshold voltage shift (ΔV th ), and Al 2 O 3 /GaN interface charge density (N it ).

Metal-oxide-semiconductor (MOS) structure represents an important gate technology in GaN HEMTs. As oxide/semiconductor interface quality is remaining reliability concern, several techniques for determination of interface state density (D it ) has been proposed. In the literature, the hysteresis in C-V sweeps (or V th shift, ΔV th ) is often interpreted as D it in particular energy range in the semiconductor band-gap. In this work, we critically assessed a relevancy of relation between ΔV th (measured at 25 and 125 ° C) and experimentally determined D it distribution, to point out possible pitfalls in the data interpretation. D it distributions were measured by combination of complementary techniques and ID simulations applied to state-of-the-art MOS-HEMTstructures with Al 2 O 3 films grown by ALD on AlGaN/GaN heterostructures. It is demonstrated that, apart from interface traps, also other parasitic effects related to border traps and oxide bulk traps can have dominant impact on ΔV th -This means that ΔV th could not be solely related to D it , unless negligibility of other relevant effects is confirmed.

GaAs-based heterostructures exhibit excellent carrier transport properties, mainly the high carrier velocity. An AlGaAs-GaAs heterostructure field-effect transistor (HFET) with an InGaAs channel was prepared using metal-organic chemical vapor deposition (MOVPE). An AlOx layer was formed on the AlGaAs barrier layer by the air-assisted oxidation of a thin Al layer deposited in-situ in an MOVPE reactor immediately after AlGaAs/InGaAs growth. The HFETs and MOSHFETs exhibited a very low trap state density in the order of 10(11) cm(-2) eV(-1). Capacitance measurement yielded no significant difference between the HFET and MOSHFET structures. The formation of an AlOx layer modified the surface by partially eliminating surface states that arise from Ga-and As-based native oxides. The presence of an AlOx layer reflected in a reduced gate leakage current, which was evidenced by the two-terminal transistor measurement. Presented preparation procedure and device properties show great potential of AlGaAs/InGaAs-based MOSHFETs. (C) 2016 Elsevier B.V. All rights reserved.

The oxide/semiconductor interface state density (Dit) in Al2O3/AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistor (MOS-HEMT) structures with gate oxides grown by atomic layer deposition at low deposition temperature is analyzed in this work. MOS-HEMT structures with Al2O3 gate oxide were deposited at 100 and 300 °C using trimethylaluminum precursor and H2O and O3 oxidation agents. The structures were found to show negative net charge at oxide/barrier interface with density (Nint) of 1013 cm−2, which was attributed to the reduction of barrier surface donor density (NDS). Dit was determined using capacitance transient techniques, and the results were assessed by the simulations of the capacitance–voltage characteristics affected by interface traps. The results indicate a lower interface quality of the sample with Al2O3 grown using O3 agent compared to those with H2O, even though the former provided lowest gate leakage among the analyzed structures. Moreover, to uncover the NDS nature, Dit distributions determined here were compared to that reported previously on devices with Nint close to zero, i.e., with fully compensated surface barrier polarization charge by NDS [Ťapajna et al., J. Appl. Phys. 116, 104501 (2014)]. No clear correlation between Dit and NDS was concluded, indicating the nature of NDS to be different from that of interface states in the energy range analyzed here.

Oxide/semiconductor interface trap density (Dit) and net charge of Al2O3/(GaN)/AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistor (MOS-HEMT) structures with and without GaN cap were comparatively analyzed using comprehensive capacitance measurements and simulations. Dit distribution was determined in full band gap of the barrier using combination of three complementary capacitance techniques. A remarkably higher Dit (∼5–8 × 1012 eV−1 cm−2) was found at trap energies ranging from EC-0.5 to 1 eV for structure with GaN cap compared to that (Dit ∼ 2–3 × 1012 eV−1 cm−2) where the GaN cap was selectively etched away. Dit distributions were then used for simulation of capacitance-voltage characteristics. A good agreement between experimental and simulated capacitance-voltage characteristics affected by interface traps suggests (i) that very high Dit (>1013 eV−1 cm−2) close to the barrier conduction band edge hampers accumulation of free electron in the barrier layer and (ii) the higher Dit centered about EC-0.6 eV can solely account for the increased C-V hysteresis observed for MOS-HEMT structure with GaN cap. Analysis of the threshold voltage dependence on Al2O3 thickness for both MOS-HEMT structures suggests that (i) positive charge, which compensates the surface polarization, is not necessarily formed during the growth of III-N heterostructure, and (ii) its density is similar to the total surface polarization charge of the GaN/AlGaN barrier, rather than surface polarization of the top GaN layer only. Some constraints for the positive surface compensating charge are discussed.

Drain current trapping characteristics were systematically analyzed and compared on normally-off p-GaN/AlGaN/GaN HEMTs for power switching applications, grown on AlGaN/GaN double and Fe-doped GaN single heterostructures with and without Ar implantation into n-SiC substrate. Spatial location of traps was studied using comparison between trapping behaviour of devices with and without field-plate electrode and correlation between early-stage degradation modes and trapping behaviour. Our results indicate that for HEMTs grown on DH buffer, trapping process with time constant in the seconds range may be mitigated by Ar implantation into SiC.

DC and transient self-heating effects are investigated in normally off AlGaN/GaN transistors designed for a high-power operation. Electrical and optical methods are combined with thermal simulations; 2-mu s-long voltage pulses dissipating about 4.5 W/mm are applied on four different transistor structures combining GaN or AlGaN buffer on an n-type SiC substrate with or without Ar implantation. Transistors with only 5% Al mass fraction in the buffer show almost a threefold increase in the transient self-heating if compared with devices on the GaN buffer. On the other hand, 2-mu s-long pulses were found not to be long enough for the Ar-implanted SiC substrate to influence the device self-heating unless AlGaN composition changes. In the dc mode, however, both the buffer composition and Ar implantation significantly influence the self-heating effect with the highest temperature rise for the transistor having the AlGaN buffer grown on the Ar-implanted SiC. We point on possible tradeoffs between the transistor high-power design and the device thermal resistance.

The trapping phenomena in GaN metal-oxide-semiconductor high-electron mobility transistor structures with 10 and 20-nm thick Al2O3 gate dielectric grown by metal-organic chemical vapor deposition were deeply investigated using comprehensive capacitance-voltage measurements. By controlling the interface traps population, substantial electron trapping in the dielectric bulk was identified. Separation between the trapping process and the interface traps emission allowed us to determine distribution of interface trap density in a wide energy range. Temperature dependence of the trapping process indicates thermionic field emission of electrons from the gate into traps with a sheet density of ∼1013 cm−2, located a few nm below the gate.

We analyze the fixed oxide charge in Al2O3 grown by thermal and plasma enhanced ALD at 100 and 200 °C using capacitance-voltage measurements on MOS structures with different Al2O3 thickness. For both ALD techniques and deposition temperatures, Al2O3 shows negative fixed oxide charge with density in the range of 2-7×1012 cm-2, most likely located at the Al2O3/SiO2 interface as inferred from the linear dependence of flat-band voltage on Al2O3 thickness. The break-down field ranges from 4 to 8 MV/cm illustrating a high quality of the Al2O3 layers. Post-deposition annealing was found to stabilize the Al2O3 dielectric constant determined to be similar to 9. Control of the negative Al2O3 fixed charge represents a promising way to e.g. enhance the threshold voltage shift of GaN based MOS heterostructure FETs towards normally-off operation.