We propose a physical design methodology for synthesis using soft hierarchy, interior pin placement, pre-placing critical logic, and routing techniques on a very timing- and area-challenged unit, the L2 cache, with ~20 million synthesizable transistors. In any past and present standard design at IBM, this test case would stretch all front- and back-end design tools by two to three times due to data volume, congestion and timing criticality, which opens a new avenue to explore for Large Block Synthesis flow. The results confirm the ability to deliver a design in the shortest possible schedule at ~50% of Physical Design cost while still maintaining best-of-breed quality.

POWER8™ (P8) processor is a 12-core, 649mm2, 4.2B transistor chip fabricated in IBM's 22nm SOI technology with 2.5× socket performance improvement over its 32nm predecessor, POWER7+, driven by big data application and power efficient computing. Highly distributed chip voltage regulator achieves a peak power efficiency of 90.5%. Resonant clock design is used in 13 clock meshes to achieve about 4% power savings for the chip. This chip is built with three thin-oxide transistor Vt for power/performance benefit and one thick-oxide transistor to enable high-voltage circuits. In order to achieve desired performance within the power envelop, P8 is built with 7 input voltages and 15-layers of metals along with the use of pulsed-clock latches. The P8 has 15823 total pads: 5982 power, 7742 ground and 2099 signal. The power/performance complexity, size of the die, along with high operating frequency presented significant challenges to complete the design on an aggressive schedule. Some of the design methodology and implementation innovations in P8 have been presented in this paper, with an emphasis on macro design topologies (custom, array and synthesis), timing methodology, as well as the electrical characterizations performed in the chip bring-up lab.