Shrinking transistor sizes allow increased logic complexity in modern processors, but smaller dimensions increase power density and require reduced maximum voltage $(\text{VDD}_{\text{MAX}})$ for reliability; this can severely limit the performance achievable in new technologies. Three techniques increase performance of the POWER10™ processor, built on Samsung 7nm technology, within these constraints: (a) a Workload-Optimized Frequency (WOF) algorithm to maximize frequency within the power envelope, (b) Core Logic Voltage (VDD) droop mitigation using a Digital Droop Sensor (DDS) with core throttling, and (c) Undervolt - a voltage control loop using the DDS to offset loadline uplift and voltage gradients and noise effects to maintain VDD below $\text{VDD}_{\text{MAX}}$ .

The POWER10™ processor designed for enterprise workloads contains 16 synchronous SMT8 cores (Fig. 2.4.1) coupled through a bi-directional high-bandwidth race-track [1] [2]. A SMT8 core with its associated cache is called a core chiplet, and a pair of core chiplets forms a 39.4mm2 design tile. Designed in a 7nm bulk technology, the 602mm2 chip (0.85× of POWER9™ [3]) has nearly 18B transistors, 110B vias and 20 miles of on-chip interconnect distributed across 18 layers of metal: 8 narrow-width layers for short range routes, 8 medium-width layers for high performance signals and two 2160nm ultra-thick metal (UTM) layers dedicated for power and global clock distribution. There are 10 input voltages as shown in Fig. 2.4.1: core/cache logic (Vdd), cache arrays (Vcs), nest logic (Vdn), two PHY voltages (Vio, Vpci), stand-by logic (Vsb), a high-precision reference voltage (Vref), DPLL voltage (VDPLL), analog circuitry voltage (VAVDD), and an interface voltage (V3P3). The C4 array contains 24477 total connections (1.25× of [3]) with 10867 power, 11879 ground and 1731 signal connections. A core and its associated L2 cache are power-gated together, while the L3 cache is power-gated independently.

Digital droop sensors (DDSs) with core throttling mitigate microprocessor voltage droops and enable a voltage control loop (undervolting) to offset loadline uplift plus noise effects, protecting reliability $V_{\mathrm {DDMAX}}$ . These combine with a runtime algorithm for workload optimized frequency (WOF) that deterministically maximizes core frequency. The combined effect is demonstrated across a range of workloads, including SPEC, and provides up to a 15% frequency boost and a 10% reduction in core voltage.

Modern multicore microprocessors require attentive development to energy requirements when maximizing power-performance efficiency and ensuring reliable plus scalable functionality. IBM POWER9 relies on extensive modeling to identify representative workloads used when analyzing thermal design power and regulator design power against product requirements. Compounding benefits of circuit optimizations applied to the diverse subcomponents of the chip results in lower power cores, caches, and memory/IO interconnect. Specific dc- and ac-current analyses ensure proper definition of chip specifications for system voltage and current delivery. Finally, a systematic exploration of microbenchmarks on intermediate and final POWER9 hardware provides insight into processor core requirements while validating model accuracy.

Cognitive computing and cloud infrastructure require flexible, connectable, and scalable processors with extreme IO bandwidth. With 4 distinct chip configurations, the POWER9 family of chips delivers multiple options for memory ports, core thread counts, and accelerator options to address this need. The 24-core scale-out processor is implemented in 14nm SOI FinFET technology [1] and contains 8.0B transistors. The 695mm 2 chip uses 17 levels of copper interconnect: 3-64nm, 2-80nm, 4-128nm, 2-256nm, 4-360nm pitch wiring for signals and 2- 2400nm pitch wiring levels for power and global clock distribution. Digital logic uses three thin-oxide transistor V t s to balance power and performance requirements, while analog and high-voltage circuits eliminated thick-oxide devices providing process simplification and cost reduction. By leveraging the FinFET's increased current per area, the base standard cell image shrunk from 18 tracks per bit in planar 22nm to 10 tracks per bit in 14nm providing additional area scaling.

The POWER9™ Processor in 14 nm SOI FinFET technology makes use of 7 different families of arrays. This paper gives an overview on advantages of different implementations, focusing on two key innovations introduced with this processor generation: Fast and low-latency write assist schemes for single-voltage performance arrays, as well as a new methodology, the synthesized soft arrays, to enable significant improvements for small array structures in both area and design efficiency.

Increasing transistor counts in modern processors can create instantaneous changes in current, driving nanosecond-speed supply voltage (V DD ) droops that require extra guardband for correct product operation. The POWER9 processor uses an adaptive clock strategy to reduce timing margin needed during power supply droop events by embedding analog voltage-droop monitors (VDMs) that direct a digital phase-locked loop (DPLL) to immediately reduce clock frequency in response.

The POWER9TM family of chips is fabricated in 14-nm silicon-on-insulator finFET technology using 17 levels of copper interconnect. The 695-mm2 24-core microprocessor features a new core based on an execution slice microarchitecture. The chip contains 8 billion transistors and has 120 MB of eDRAM L3 cache. The processor features an adaptive clock strategy to reduce timing margin needed during power supply droop events by embedding analog voltage-droop monitors that direct a digital phase-locked loop to immediately reduce clock frequency in response to a droop event. The scale-out chip IO subsystem supports up to 300-GB/s accelerator bandwidth using new 25-Gb/s links, 48 lanes of PCIeGen4 totaling 192 GB/s, eight ports of 2667 MT/s DDR4, and 256 GB/s of symmetric multiprocessor (SMP) interconnect. The scale-up chip adds additional SMP bandwidth and replaces the DDR4 memory interface with eight ports of differential memory interfaces with 230 GB/s of bandwidth resulting in 12.9 Tb/s of total off-chip bandwidth.

This paper presents an approach to solving the problem of generating a single statistical timing macro-model or abstract for a chip component, and subsequently applying it smartly at multiple voltage domain conditions at a parent level of hierarchy during hierarchical timing. This approach avoids overheads in a traditional approach of having either multiple abstracts for the same component corresponding to different voltage domains, or having excessive guard-bands in a single common abstract. Results are presented for a set of test-cases including industrial microprocessor units. The results exhibit more than 200 picoseconds of improved accuracy ( both pessimism reduction and optimism avoidance) when using the proposed solution in comparison to an approach that assumes a single voltage domain compatible abstract.

The demand for ultra-high speed transceivers continues to rise exponentially due to the insatiable demand for high-throughput interconnect. Standards between 25 and 32Gb/s are rapidly approaching maturity, and available products and IPs at these rates are iterating to push down power while extending channel-loss recovery limits. Predictably, specifications are now in early stages for extending per-lane bandwith to between 40 and 64Gb/s. Meeting these 25Gb/s+ targets, especially for long-reach applications, is stressing the capabilities of both the underlying circuitry and the communication channels, and has caused significant rethinking of the overall system and circuit architectures for these links. In particular, the debate about multi-level (PAM4) versus binary (PAM2) signaling and which path offers the best energy-efficiency/data-rate scalability has returned to the foreground. Similarly, the emergence of high-speed ADCs with sufficient resolution for link applications has driven renewed interest in DSP-based approaches, while other efforts have pushed more analog/mixed-signal link components to over 60Gb/s/lane. To further ensure low BER operations, sophisticated coding such as FEC is brought into the discussion. Even in the domain of optical communications, significant challenges related to the bandwidth capabilities of the optical devices as well as the back end processing are currently being addressed. In fact, some of the highest speed optical links are limited by the short electrical interconnect between the driver circuitry and the optical module itself. This forum presents state-of-the-art I/O techniques enabling such high line rates across both optical and electrical interfaces as well as a number of emerging standards such as 802.3bj, various flavors of CEI, and HMC (hybrid memory cube).

The IBM POWER8™ processor is a 649-mm2, 4.2-billion transistor, high-frequency microprocessor fabricated in the IBM 22-nm silicon on insulator (SOI) technology with embedded dynamic random access memory (eDRAM) and 15 layers of metal. With its twelve architecturally enhanced, eight-way multithreaded cores, 96-MB high-bandwidth shared third-level cache, and increased on and off-chip bandwidth, the POWER8 processor delivers industry-leading performance. This paper describes the circuit techniques and design methodologies that were employed for implementing this chip and that allowed it to maintain the power dissipation at the level of its predecessor while delivering a threefold increase in per-socket performance. Among the innovative technologies employed by the processor are resonant clocking, on-chip per-core voltage regulation, and enhanced eDRAM arrays.

POWER8™ (P8) processor is a 12-core, 649mm2, 4.2B transistor chip fabricated in IBM's 22nm SOI technology with 2.5× socket performance improvement over its 32nm predecessor, POWER7+, driven by big data application and power efficient computing. Highly distributed chip voltage regulator achieves a peak power efficiency of 90.5%. Resonant clock design is used in 13 clock meshes to achieve about 4% power savings for the chip. This chip is built with three thin-oxide transistor Vt for power/performance benefit and one thick-oxide transistor to enable high-voltage circuits. In order to achieve desired performance within the power envelop, P8 is built with 7 input voltages and 15-layers of metals along with the use of pulsed-clock latches. The P8 has 15823 total pads: 5982 power, 7742 ground and 2099 signal. The power/performance complexity, size of the die, along with high operating frequency presented significant challenges to complete the design on an aggressive schedule. Some of the design methodology and implementation innovations in P8 have been presented in this paper, with an emphasis on macro design topologies (custom, array and synthesis), timing methodology, as well as the electrical characterizations performed in the chip bring-up lab.

POWER8™ is a 12-core processor fabricated in IBM's 22 nm SOI technology with core and cache improvements driven by big data applications, providing 2.5× socket performance over POWER7+™. Core throughput is supported by 7.6 Tb/s of off-chip I/O bandwidth which is provided by three primary interfaces, including two new variants of Elastic Interface as well as embedded PCI Gen-3. Power efficiency is improved with several techniques. An on-chip controller based on an embedded PowerPC™ 405 processor applies per-core DVFS by adjusting DPLLs and fully integrated voltage regulators. Each voltage regulator is a highly distributed system of digitally controlled microregulators, which achieves a peak power efficiency of 90.5%. A wide frequency range resonant clock design is used in 13 clock meshes and demonstrates a minimum power savings of 4%. Power and delay efficiency is achieved through the use of pulsed-clock latches, which require statistical validation to ensure robust yield.

POWER8™ delivers a data-optimized design suited for analytics, cognitive workloads, and today's exploding data sizes. The design point results in a 2.5x performance gain over its predecessor, POWER7+™, for many workloads. In addition, POWER8 delivers the efficiency demanded by cloud computing models and also represents a first step toward creating an open ecosystem for server innovation.