A GROWING NUMBER of safety-critical and mission-critical applications require extremely reliable operations. In automotive electronics and hyperscale data centers, the ever-increasing demands for exceptionally high quality will push for solutions relying largely on manufacturing design for test (DFT) throughout the entire silicon lifecycle, including in-system and in-field operations. Advanced technology nodes, especially those at 7 nm and below with 3D multi-die packaging, observe new complex parametric defects and reliability risks related to aging. Cloud service providers have reported silent data corruption errors caused by subtle IC defects producing faulty results only occasionally what makes them extremally difficult to find [1], [2]. A closer examination of the problem reveals underlying issues [3]: test escapes due to marginalities as well as latent or aging defects, early-life failures, random defectivity, and environmental conditions that lead to malfunctions.

Automotive designs demand the highest possible test coverage for safety and reliability. One approach is to add as many test points as possible to the circuit. To avoid increasing the die size, test point sharing can be used to maximize the number of test point nodes while using fewer test point flops. While test point sharing reduces area overhead, extra wiring is needed leading to congestion which again limits the number of test points that can be added. This paper presents a method to reduce wiring congestion when sharing a large number of test points. Our method also reduces the impact sharing can have on fault coverage. Test point sharing is optimized in the physical implementation tool to reduce wiring and congestion leading to improvements in PPA. Results from five automotive designs show up to a 67% reduction in wiring for test point logic, an average 24% reduction in congestion, and improvements in PPA. Alternatively, one can increase the number of test points and achieve a 1.62% improvement in LBIST coverage without introducing additional congestion or impacting PPA.

The articles in this special section were presented at the 2019 IEEE VLSI Test Symposium (VTS) that was held in Monterey, CA. The 2019 VTS Conference laid particular emphasis on enlarging its scope by soliciting submissions on testing, reliability, and security aspects on the following hot topics: approximate computing, neuromorphic computing, and quantum computing.

Scan compression is a critical technology for addressing the rapid rise of test cost without sacrificing coverage requirements. It has become widely adopted throughout the semiconductor industry but is facing challenges. The rise of safety-critical semiconductors demands not just high coverage, but also the ability to verify that the design is working in the field. Traditional approaches have used discrete scan compression and LBIST, as shown by Figure 1. Issues with additional area overhead and routing congestion limit the effectiveness of this architecture.

Multiple defects are prevalent in early stages of yield improvement for a new technology. When a logic diagnosis procedure is applied to a faulty unit that contains a multiple defect, it sometimes produces a large set of candidate faults. Such a set includes extra candidates that do not match the defect present in the faulty unit. An earlier study indicates that a logic diagnosis procedure may prefer certain faults as candidate faults, causing them to appear as extra candidates in many sets of candidate faults. This points to the possibility of using a small number of observation points to eliminate extra candidates that appear often. This paper takes advantage of this observation to improve the quality of diagnosis by placing observation points. Experimental results for benchmark circuits demonstrate the effectiveness of observation points in reducing large sets of candidate faults.

Test Compression and logic built-in self-test (LBIST) are proven DFT solutions to address the quality and safety requirements of automotive electronics but their high impact to backend physical implementation can be a huge barrier to successful adoption. Unified compression is a new approach that unifies scan compression and LBIST. It leverages recent innovations in Physical DFT Synthesis to solve routing congestion and area issues from traditional discrete approaches and paves the road to high-quality testing. Area savings of 35-47%, and scan wirelength savings of 63-77% for the same scan chain length can be achieved while reducing test application time by 50%.

TSMC has developed the Chip-on-Wafer-on-Substrate (CoWoS®) process as a design paradigm to assemble silicon interposer-based 3D-ICs. To reach quality requirements for volume production, several test challenges related to 3D-ICs need to be addressed. This chapter describes the test and diagnosis solutions for the challenges that were faced in designing a CoWoS® process-based heterogeneous memory-on-logic and logic-on-logic 3D-IC. The objective of this design was to find the stacking process weaknesses in creating a stacked die system consisting of multiple dies in different technologies (logic and memory). It is also used to demonstrate the strength of the stacking capability when dies to be stacked are sourced from different vendors. The design contains three dies: system-on-chip die (logic), DRAM die (logic), and JEDEC WideIO DRAM die (memory). The chapter demonstrates how the design-for-diagnosis features implemented on the logic die were used to isolate interconnect testing failures.

Test Compression ratios are currently stalled at 100-200X. A new 2-dimensional physically-aware sequential Compressor-Decompressor design addresses the severe wiring congestion as well as the test coverage droop and pattern spike at the highest compression ratios. Results on some commonly used industrial designs shows a 2X reduction in routing overhead and congestion associated with Test Compression logic. The target test coverage is maintained while achieving up to 3.7X reduction in test data volume and test application time beyond the conventional methods.

This paper presents a novel approach for performing diagnosis in test access mechanisms (TAM) architectures based on time domain multiplexing and serial scan shifting. These TAM architectures allow efficient application of low power compressed patterns to individual embedded cores present in SoCs using limited pins. The proposed diagnosis approach relies on the connectivity information of the TAM architecture to map SoC level failures to a particular embedded core. These TAM architectures allow high level of diagnosis resolution and performance.

This paper proposes a design-for-test architecture for efficient testing of 3-D ICs. The DfT architecture supports multiple dies, test data compression, and embedded cores. Commercial EDA tools are used to implement the DfT architecture.

Inter-die connections in 2.5D-and 3D-stacked ICs require at-speed testing as their dynamic performance is crucial to the performance of the stack as a whole. In order to test at mission-mode speed and benefit from the already existing clock distribution network, our at-speed test approach for inter-die connections targets the entire register-to-register path that includes the interconnect. This forces the launching and capturing wrapper cells to be shared with functional flip-flops. In some designs, this unavoidably leads to some 'shore logic': a, typically small, amount of combinational logic outside the die's wrapper boundary register. This paper describes how we have adapted a previously developed 3D-DfT architecture and corresponding EDA tool flows to support at-speed interconnect testing, also in the presence of such 'shore logic'. The adaptations affect the DfT insertion of wrapper cells, the boundary model extraction, and the interconnect test pattern generation.

As chip design sizes continue to increase and they contain multiple instances of large and small cores, there is a need for a chip test architecture that allows efficient chip-level tests to be created while also reducing the memory and CPU time needed to create the tests. We define a hierarchical and core-based architecture for generating tests for cores and migrating them to the chip. This architecture allows testing multiple instances of the same core for the same cost as testing a single instance. The architecture also allows testing multiple instances of different cores as well. Memory use is kept low by generating tests for cores out of context and migrating them to the chip. We never have to build a full gate-level chip ATPG model. We show results of pattern count reduction possible when targeting multiple cores simultaneously.

Summary form only given, as follows. The push for portable, battery-operated, and “cool-and-green” electronics has elevated power consumption as the defining metric of integrated circuit (IC) design. Testing ICs built for such applications requires judicious consideration of test power implications on various aspects of the design cycle (e.g., packaging and power grid design), test engineering (multi-site ATE power supply limitations and board design), power-aware test planning (DFT and ATPG), and developing the enabling EDA tool infrastructure (SW for estimation, reduction and lowpower test generation). Physically-aware low-power test techniques are also becoming important for accuracy and hot-spot minimization, especially for designs at 22nm and below. Furthermore, with power optimization and power management techniques becoming “de-facto” in almost all 45nm and lower chips, systematic testing of these structures and the device in the presence of these structures becomes mandatory. This tutorial is intended to provide an in-depth and up-to-date understanding of low-power IC testing covering (a) dimensions of power-aware testing, (b) methods for test power analysis and signoff, (c) techniques for controlling test power consumption and (d) test of power managed designs. Case-studies illustrating industrial design deployment practices and existing EDA vendor support will be outlined to illustrate capabilities and gaps in the state-of-the-art.

Low-power testing has become a need for modern designs due to rapid increasing of power density with further shrinking of feature size into nanoscale designs. In spite of low-power design efforts and low-power ATPG adopted in common test flows, excessive power dissipation and instant peak current cannot be necessarily avoided during test application. There is a need for fast peak power detection for test vectors. The test industry lacks such efficient solution. In this work, we propose a fast test power analysis methodology. By reading and processing layout data and other supporting files such as parasitic files, the proposed analysis engine performs a simplified power grid analysis with layout partition and provides following power results for each test cycle: switching activity, absolute power, hot spot contour map, absolute current estimation on power pads. The proposed flow was verified on industry designs and proved to be very efficient than using commercial power sign-off solutions for test power analysis.