Increasing complexity of digital and mixed-signal systems makes establishing the authenticity of a chip to be a challenging problem. We present a new terahertz testing technique for non-destructive identification of genuine integrated circuits, in package, in-situ and either with no or under bias, by measuring their response to scanning terahertz and sub-terahertz radiation at the circuit pins. This novel, patent pending non-invasive nondestructive technology when merged with Artificial Intelligence (AI) engine will evolve and self-improve with each test cycle. By establishing and AI processing of the THz scanning signatures of reliable devices and circuits and comparing this signatures with devices under test using AI, this technology could be also used for reliability and lifetime prediction.
This work presents various device self-heating temperature sensing techniques and discusses their application in device reliability projection. Details of sensor design, technology choice, layout and ambient temperature impact on measurement results are discussed. The sensors produce excellent results which were confirmed through TCAD thermal simulation. Self-heating was studied by varying the number of fins per active region and proximity of sensor to heater was investigated. While most data presented here is on FinFET technology the learning and measurement techniques are applicable to planar technologies. Front-end-of-line (FEOL) reliability mechanism, hot carrier injection (HCI) was studied to show that self-heating effects can impact measurement results and recommendations are given on how to mitigate them. Self-heating is also studied for logic circuits by utilizing ring oscillators with several densities and stage counts to show that self-heating is considerably lower compared to constant voltage stress conditions conducted on discrete structures.
The power limits due to thermal runaway of a germanium PIN photodiode as the O-band $(\lambda\sim\mathbf{1300\ nm})$ photodetector component of a silicon photonics technology were characterized under elevated stress conditions. A simplified model is used to project to use condition.
We introduce a new Build In Test (BIT) signature generator for functional verification and output classification of RF integrated circuits. The proposed circuit is a single rectifier-based MOS transistor, with the substrate and gate independently biased to control source terminal voltage range, followed by a passive RC filter. The proposed technique correlates the Circuit Under Test (CUT) characteristics with the dc voltage provided at the output of the BIT circuit. The output from the proposed circuit is used as signature from which we verify the performance specifications and also characterize the CUT output waveform with respect to amplitude and shape. In normal operation the proposed low cost test scheme ensures the minimum effect at the performance of the measured circuit under test since the only additional load is the source of the MOS transistor attached to it.
In-memory computing is a propitious solution for overcoming the memory bottleneck for future computer systems. In this work, we present the testing and validation considerations for a programmable artificial neural network (ANN) integrated within a phase change memory (PCM) chip, featuring a Nor-Flash compatible serial peripheral interface (SPI). In this paper, we introduce our method for validating the circuit components specific to the ANN application. In addition, high-density in-memory multi-layer ANNs cannot be manufactured without testing and repair of the memory array itself. Therefore, design for testability (DFT) features commonly used in commodity or embedded memory products must be maintained as well. The combination of these two test/characterization steps alleviates the need to test the actual inference functionality in hardware.
This article presents an artificial neural network-based signal probability predictor for VLSI circuits which considers reconvergent fan-outs. Current testability analysis techniques are useful for inserting test points to improve circuit testability, but reconvergent fan-outs in digital circuits creates inaccurate testability analysis. Conventional testability analysis methods like COP do not consider reconvergent fan-outs and can degrade algorithm results (e.g., test point insertion), while more advanced methods increase analysis time significantly. This study shows training and using artificial neural networks to predict signal probabilities increases post-test point insertion fault coverage compared to using COP, especially in circuits with many reconvergent fan-outs.
PIM is a form of intermodulation distortion that occurs in passive components. It is an unwanted signal created by the mixing of two or more RF signals, caused by the nonlinearity of the passive components in the RF path. PIM has become a big concern in the wireless and communication industry, with the introduction of 5G standards. The most demanding requirement of the linearity of the switches in an RF system is the out-of-band blocking performance. The blocking characteristic is a measure of the receiver's ability to pick up the wanted signal in the presence of an unwanted interfering signal, without causing a degradation in the performance. The rise of unwanted signals in the receiver path increase the noise level of the receiver, thereby degrading the quality of the communication signals as well as affecting the receiver sensitivity. The paper describes the way PIM measurements are performed in our lab and highlight how Multiband PIM measurements are carried out in a very efficient way, saving the time invested in setup, calibration and measurements of data, using meticulous techniques which ultimately lead to a better result.
Mathworks has developed a CPU surrogate interface for FPGAs using the common AXI bus as used by Xilinx and Altera. This FPGA IP block is instantiated as an optional control port into users base design. The IP block only requires JTAG and a system clock to provide full system test access.
In internet of things (IoT), ring oscillator physical unclonable functions (ROPUFs) are utilized for designing the wireless sensors against malicious invasive-attacks. However, the ROPUF sensors are not sufficiently secure since there are strong linear relationships between the supply voltage and the oscillating frequencies of the ring oscillators of the ROPUFs. In order to demonstrate the vulnerability of the ROPUF sensors, in this paper, a hardware Trojan attack is performed by inserting a sequential Trojan circuit into the ROPUF sensors to leak the critical oscillating frequency. As shown in the result, analyzing about 200,000 number of leaked data with machine learning techniques are sufficient to crack a 128-bit Trojan-infected ROPUF sensor. Ultimately, so as to combat the hardware Trojan attack, a Trojan detection methodology is proposed by monitoring the statistical distribution of sensed data in real-time.
This article analyzes and rationalizes the capabilities of inversion-based test points (TPs) when implemented in lieu of control-0/1 TPs. With upward scaling of transistor density, delay faults can be masked when using pseudo-random tests with control-0/1 (“conventional”) TP architectures. This study finds delay fault coverage can be improved using inversion TPs in logic circuits using pseudo-random tests without negatively impacting stuck-at fault coverage.
Charge Trap Transistor One Time Programmable Memories were introduced in 14nm as a secure non-volatile memory. This paper highlights some of the test features and complexities that were modeled in a Verilog behavioral model.
This paper is a case study of diagnostic techniques used to debug a particularly difficult fail in a multi-port register file memory that appeared to increase its minimum functional voltage (VMIN) over time. Some of the debug techniques used involved Array Built-In-Self Test (ABIST) before and after chips in burn in, CPA (Critical Parameters Analysis), PEM (Photon Emission Microscopy), PICA (Picosecond Image Circuit Analysis) and PFA (Physical Failure Analysis).
Convolutional neural network (CNN) algorithms are utilized to build a machine learning block to assist the optimizations of voltage noise, temperature distribution, and security of multi-phase on-chip switched-capacitor (SC) voltage converters. All the random sequences generated by the pseudorandom number generator (PRNG) are fed into the designed machine learning block in an SC converter sequentially to filter the unsatisfactory sequences. The results show that the maximum amplitude of the voltage noise and the highest temperature of the SC converter are reduced by 68.98% and 12.07%, respectively, while a negligible security degradation is achieved under the assistance of machine learning.
In this paper, we propose a simplified on-chip calibration method for multi-port devices to de-embed the unwanted but unavoidable parasitics introduced by the probing pads as well as the effects originating from redundant feeding lines. The traditional TRL (Thru, Reflect, Line) calibration technique for single-ended two-port device is extended to a classic on-chip branch-line coupler that can be decomposed as the odd-and even-mode equivalent circuit. Accordingly, the TRL calibration standards in the balanced format are designed as well. As a final step, 4-port single-ended S-parameters of device under test (DUT) are reconstructed through its de-embedded odd-and even-mode S-parameters. To validate the efficacy of our proposed method in extracting S-parameters of DUT, models in HFSS, such as the branch-line coupler with probing pads, and modified TRL calibration standards are generated. After performing the de-embedding procedures with the proposed calibration method in this paper, the extracted S-parameters agree well with the simulated S-parameters of DUT without adding any pads and feeding lines for measurement.
With the advent of built-in self-test (BIST) in analog and RF circuits, it is essential that the fault coverage of potential BIST solutions be evaluated before they are deployed. However, large scale fault simulations are often infeasible even when considering the extensive computational power available today. Fault simulations are more challenging for devices that contain frequency transformation, such as phased locked loops (PLLs) or mixers. Thus, a mixed-mode simulation is necessary that captures fault behavior at the lower levels of the hierarchy and propagates this information to the system-level. Mixed-mode simulators, such as Verilog-A, can be used for evaluating nominal circuit behavior but falls short when evaluating faulty circuit behavior. This paper presents a macro modeling approach for mixed-signal circuits through a case study of voltage controlled oscillators (VCOs) used in PLLs. The evaluated BIST technique is the measurement of the phase transfer function from the input to the output. This requires a long transient simulation due to the need to capture the high frequency behavior of the PLL while covering the settling time of the low-frequency filter and VCO input. As the ratio of the output to the input frequency increases, simulation time also increases, making the analyses prohibitively expensive for some cases. In this paper, we build a MATLAB/Simulink model of the VCO and PLL, which is also designed and simulated at the transistor level using the FinFET technology. By modeling free running frequency, sensitivity, duty cycle, non-linearity, and phase noise characteristic of the VCO, we show that both PLL simulations, one using Spice, and one using the proposed macromodeling technique along with Simulink, match in response whereas the proposed approach only takes a fraction of time of Spice simulations.
With the density increase of today's printed circuit board assemblies (PCBA), the electronic test methods reached their limits, in the same time the requirements of high reliability and robustness are greater. Original equipment manufacturers are obliged to reduce the number of physical test points and to find better-adapted test methods. Current test methods must be rethought to include a large panel of physical phenomena that can be used to detect electrical defects of components, absence, wrong value, and shorts at component level on the board under test (BUT). We will present the possibility of using electromagnetic signature to diagnose faulty components contactlessly. The technique consists in using small diameter near electromagnetic field probes, which detect the field distribution over powered sensitive components. A giant magnetoresistance (GMR) sensor was used as well to detect variations in low frequency components. The loading of the BUT is specifically chosen to enhance the sensitivity of the EM measurements. Reference EM signatures are extracted from a fault-free circuit, which will be compared to those extracted from a sample PCBA in which we introduced a component level defect by removing or changing the value of critical components. As a result, we will show that the amplitude of a specific harmonic acts as a sensing parameter, which is accurately related to the variation of the component value.
The cost of semiconductor test is often strongly related to the die test time. Reducing this time is always a goal for both the fab customer as well as the semiconductor test house. Techniques to achieve test time reduction have included the use of dedicated hardware to perform certain test functions. While these techniques are effective, they can be time consuming to develop and this effort is often a deterrent to their development and use. This paper describes how a Field Programmable Gate Array (FPGA) accelerator can be used to process wafer test data. Historically, the use of FPGAs required a skilled digital designer to create the necessary logic to implement the intended test processing hardware. With OpenCL, however, the addition of hardware acceleration can be accomplished with traditional software coding. The amount of time required to deliver the test solution can be reduced from multiple weeks (or longer) to just a few days. With OpenCL, the ability to use hardware acceleration is brought to test engineers who do not have skills to designs FPGA logic.
More stringent defect detection requirements have led to the creation of new fault models, such as the cell-aware fault model, that attempt to model defects that might be missed by traditional test sets. Unfortunately, the resulting test sets can be long, and thus we have explored a DFT-based approach to reduce test time by harnessing scan shift cycles for defect detection. However, even advanced fault models may still miss some defects (for example, defects between standard cells). The n-detect test approach attempts to detect such defects fortuitously by increasing the number of times that simpler faults (e.g. stuck-at faults) are detected. In this paper, we investigate the ability of our DFT circuitry to provide multiple stuck-at fault detections of the hardest to detect stuck-at faults during scan shift. We will show that significant additional fault detections are possible in the circuits studied, even when only a subset of all scan chain flops are used for scan shift capture.
The increasing complexity of silicon VLSI circuits makes their comprehensive testing, determination of counterfeit parts, and predictions of reliability a growing challenge. We analyze the response of Si MOSFETs to sub-THz and THz radiation for different feature sizes and temperatures. Our results show that such testing could be expanded to develop unique response signatures for contact and channel regions for feature sizes exceeding 20 nm. They also indicate a possibility of the resonant MOSFET response to the THz radiation at cryogenic temperatures.
Multi-project wafers have lowered manufacturing costs for semiconductor prototypes, yet test costs remain high, presenting a barrier for innovation in the market. We present and analyze a low-cost test strategy for memory devices.
