We propose a simple and efficient test and analysis scheme to identify and categorize defective bits in large-scale STT-MRAM arrays using the switching voltage (V sw ) distribution from single measurement sequence for both set and reset operations. We analyzed V sw with statistical approach of complementary cumulative distribution function (CCDF) and observed a high V sw tail with low probability, similar to the ballooning feature in write error rate analyses on STT-MRAM devices. We demonstrate such ballooning feature in V sw CCDF clearly originates from devices with relatively low resistance and TMR ratio, generally attributed to the magnetic tunnel junction (MTJ) pillars with soft shorts caused by re-deposition during the patterning process. The key advantage of present test and analysis scheme is the ability to differentiate defective bits such as soft-shorted devices from normal devices directly from the arrays without reading resistances and consequently to improve the speed and efficiency of STT-MRAM product development.

In Voltage-Controlled Magnetic Anisotropy (VCMA) switching of magnetic random-access memory (MRAM), the precessional dynamics of the magnetization is behind the writing mechanism. This work aims to give a fundamental understanding of VCMA-induced precessional switching dynamics through macrospin modeling. We start investigating the effects of different voltage pulse amplitude and pulse shapes on the precessional dynamics of the magnetization. We show that high voltage does not necessarily result in a faster and a more consistent switching and that adding a few hundreds of picoseconds ramp times will have an important impact on the switching dynamics and its final state. Moreover, we perform the analysis considering two damping parameters, an unrealistically high Gilbert damping parameter for CoFeB thin films (α = 0.2) and a realistic parameter for CoFeB (α = 0.01), showing how they impact the precession dynamics.

This paper presents the Design Technology Co-optimization (DTCO) study of the 1-diode 1- Voltage controlled magnetic anisotropy (1D-1VCMA) stack, which functions as Storage Class Memory (SCM) to bridge the gap between DRAM and flash memory. The dual requirement of low sneak current and high non-linearity for bidirectional selectors in 1S-1R crossbar memories is extremely challenging to achieve practically. Moreover, the IR drop due to parasitic resistance (RPAR) results in significant degradation in the voltage across the memory element (ME) and causes write disturbance for the 1S-1R crossbar. 1D-1VCMA solves the above-mentioned issues by having low write current (Iw), (thus reducing IR drop) and increasing the number of DINs /DOUTs to improve energy/bit. Sneak current and non-linearity are also significantly improved due of the diode selector. Based on our VCMA and IGZO diode technology data and an extensive DTCO, we are able to achieve a write energy consumption of 880fJ/bit (at a delay of 40.5ns and VDD of 2V), and read energy consumption of 414fJ/bit (at a read delay of 39ns), thus showing a significant improvement over similar SCMs.

Voltage control of the magnetic anisotropy (VCMA) effect enables a voltage-mediated magnetization switching mechanism for lower-power applications. In this work, we experimentally investigate the characteristics of VCMA-induced switching and we observe a clear decrease in the critical switching voltage (Vc) at elevated temperatures. A 50% reduction in Vc is quantified when increasing the ambient temperature (T) from 300 K to 360 K. Such a T-dependence of Vc is well explained with the variations of saturation magnetization (MS), interfacial anisotropy (Ki), and VCMA coefficient (ξ). In addition, the dependences of these properties on temperature are well fitted and explained with the power law of MS(T). Our findings on the T-dependent magnetic and switching characteristics of VCMA are of technological importance for implementing VCMA in magnetic random access memory (MRAM) applications.

Voltage-gate assisted spin-orbit torque (VGSOT) writing scheme combines the advantages from voltage control of magnetic anisotropy (VCMA) and spin-orbit torque (SOT) effects, enabling multiple benefits for magnetic random access memory (MRAM) applications. In this work, we give a complete description of VGSOT writing properties on perpendicular magnetic tunnel junction (pMTJ) devices, and we propose a detailed methodology for its electrical characterization. The impact of gate assistance on the SOT switching characteristics are investigated using electrical pulses down to 400ps. The VCMA coefficient ({\xi}) extracted from current switching scheme is found to be the same as that from the magnetic field switch method, which is in the order of 15fJ/Vm for the 80nm to 150nm devices. Moreover, as expected from the pure electronic VCMA effect, {\xi} is revealed to be independent of the writing speed and gate length. We observe that SOT switching current characteristics are modified linearly with gate voltage (V_g), similar as for the magnetic properties. We interpret this linear behavior as the direct modification of perpendicular magnetic anisotropy (PMA) and nucleation energy induced by VCMA. At V_g = 1V, the SOT write current is decreased by 25%, corresponding to a 45% reduction in total energy down to 30fJ/bit at 400ps speed for the 80nm devices used in this study. Further, the device-scaling criteria are proposed, and we reveal that VGSOT scheme is of great interest as it can mitigate the complex material requirements of achieving high SOT and VCMA parameters for scaled MTJs. Finally, how that VGSOT-MRAM can enable high-density arrays close to two terminal geometries, with high-speed performance and low-power operation, showing great potential for embedded memories as well as in-memory computing applications at advanced technology nodes.

We present a detailed study of the impact of damage minimizing patterning schemes on the electrical performance of perpendicular STT-MRAM devices at array level, compatible with 22 nm CMOS technology node. By employing a novel patterning scheme involving physical ion beam etch (IBE), etchback and oxidation steps, we show reduction in switching voltage (32%), switching energy (20%) and an improvement in the reliability window (20%), as compared to the conventional physical etch. These improvements are reported in conjunction with 10-year data retention ($\Delta$), WER ∼ 1 ppm and 108 cycling on 1 kbit cells. We attribute these improvements to a significant reduction in free layer (FL) damage. Morphological studies highlighting the minimization of oxygen penetration and the subsequent bird's beak formation around the FL strongly support our understanding. These results highlight a possible tuning knob in the IBE process to improve the device performance significantly and may help to improve the tail bits.

For the first time in voltage control of magnetic anisotropy magnetic random-access memory (VCMA-MRAM), a large coefficient of ≥ 100 fJ/Vm has been demonstrated in fully integrated, BEOL compatible, magnetic tunnel junctions (MTJ). This was achieved while maintaining a high TMR (180%) and thermal stability factor ( $\Delta > 40$ ). VCMA-induced switching is also explored, showing the benefits for low power and ultrafast memory applications. This was enabled thanks to the development of a VCMA-MRAM specific free-layer (FL) which incorporates the insertion of transition metals at the CoFeB|MgO interface. The design of this FL was driven by atomistic simulations using an imec developed, non-perfect epitaxial stack model.

We study the characteristics of the precessional switching induced by voltage control of magnetic anisotropy (VCMA) in back-end-of-line (BEOL)-compatible perpendicular magnetic tunnel junction devices. Using micromagnetic simulation, we find three operation regimes differentiated by zero excess energy, lower boundary, zero energy barrier, and upper boundary. Experimentally, the switching speed (fs) is characterized by two phases: non-precession and acceleration. Non-precession is a thermal mediated phase, where fs cannot be deduced, while in acceleration, both the higher electric field (EF) and in-plane field (Bx) increase fs progressively. We find that the intrinsic thresholds can be retrieved by linear extrapolation of fs as a function of EF. Those thresholds and experimental results are in good agreement with the simulation. In addition, we numerically calculate the characteristic switching speed of 2γ*mz*Bx and verify it experimentally. This work provides insights into the VCMA-induced precessional switching, including detailed understandings of the switching mechanism and modeling of switching speed for reliable write duration control for practical applications.

We propose a deterministic VCMA writing concept that allows exclusion of the pre-read which is required in conventional VCMA write scheme. We apply it on 400°C compatible pMTJ devices with high TMR 246% and retention = 54 and demonstrate a genuine ns-scale write speed. Furthermore, we realize reliable 1.1 GHz external field-free VCMA switching with 20fJ write energy by integrating a magnetic hard mask as the in-plane magnetic field generator. An endurance of more than 10 10 cycles is achieved. Our results address the fundamental write operation challenges of the voltage-controlled MRAM technologies.

We propose a field-free switching SOT-MRAM concept that is integration friendly and allows for separate optimization of the field component and SOT/MTJ stack properties. We demonstrate it on a 300 mm wafer, using CMOS-compatible processes, and we show that device performances are similar to our standard SOT-MTJ cells: reliable sub-ns switching with low writing power across the 300mm wafer. Our concept/design opens a new area for MRAM (SOT, STT and VCMA) technology development.

We study the offset fields affecting the free layer of perpendicularly magnetized tunnel junctions. In extended films, the free layer offset field results from interlayer exchange coupling with the reference layer through the MgO tunnel oxide. The free layer offset field is thus accompanied with a shift of the free layer and reference layer ferromagnetic resonance frequencies. The shifts depend on the mutual orientation of the two magnetizations. The offset field decreases with the resistance area product of the tunnel oxide. Patterning the tunnel junction into an STT-MRAM disk-shaped cell changes substantially the offset field, as the reduction of the lateral dimension comes with the generation of stray fields by the reference and the hard layer. The experimental offset field compares best with the spatial average of the sum of these stray fields, thereby providing guidelines for the offset field engineering.

At breakdown conditions, large current flows in STT-MRAM devices. We experimentally show that this large current causes significant self-heating of 200-300°C, which impacts the reliability extrapolation to operating conditions. By measuring and analyzing breakdown at various temperatures and on different MgO thickness, we successfully incorporate self-heating into the breakdown model. We find that the 10 year lifetime is underestimated by a factor 10 3 at 63-percentile, to even 10 7 when applying percentile scaling to 1 ppm.

The increased complexity of CMOS transistor processing has led to limited scaling of high density SRAM cell at advanced technology nodes. STT-MRAM appears to be a promising candidate for replacing last level caches (LLC). This paper addresses design technology co-optimization (DTCO) of STT-MRAM technology and analyzes its viability as a LLC (compared to SRAM) for the high performance computing (HPC) domain (while maintaining a constraint of occupying merely 43.3% of SRAM macro area at identical capacities). This is the first study that breaks down a power, performance and area (PPA) comparison between SRAM and STT-MRAM based LLCs at the 5nm node. The STT-MRAM design and analysis is based on a silicon verified compact model and can be realized using 193i single patterning at the 5nm node. Our STT-MRAM design manages to achieve a nominal access latency <;2.5ns and <;7.1ns for read and write operations respectively. We also observe a clear and significant trend of increasing energy gains with respect to SRAM for increasing LLC sizes with the crossover points for STT-MRAM read and write operations at 0.4MB and 5MB respectively.

In this work, we detail a novel methodology to extract the magnetisation switching and MgO breakdown characteristics of STT-MRAM devices, from a single d.c. ramped voltage stress (RVS) measurement. This is performed by a two-step process, initially by a robust outlier screening procedure on a piecewise fit to the measured data. Subsequently, these fit results are subjected to k-means cluster analysis to elucidate the magnetisation states present, together with the voltages at which these states change, or breakdown occurs. We validate this methodology by successfully correlating our RVS results with the more widely reported pulsed-breakdown results. An application of this technique examines the impact of scaling MgO tunnel layer thickness. We demonstrate how both the switching and breakdown voltage values reduce with scaling down the MgO tunnel-layer thickness for ultra-thin MgO layers. The switching voltage reduction is more significant than the breakdown voltage reduction, which results in a gain in reliable operation margin on reducing MgO thickness.

Magnetic tunnel junctions (MTJs) with perpendicular magnetic anisotropy (PMA) have been developed for decades for spin-transfer-torque magnetic random-access memory. Common stack designs use a hard layer (HL) with strong PMA to pin the reference layer (RL) by forming a synthetic antiferromagnet through a thin nonmagnetic coupling layer. Compared to bottom-pinned MTJs, very limited progress has been made to top-pinned MTJs, especially on the RL pinning due to its inferior thermal robustness. Herein, an alternative stack design is proposed for top-pinned MTJs, i.e., a synthetic ferromagnet (SFM). In the SFM, the RL is coupled with the HL ferromagnetically through a coupling layer. Micromagnetic simulations predict the advantage of the SFM design to stabilize the RL at scaled critical dimension (CD), which is experimentally proven by the observation of an increased RL pinning field on the device level. Because of the RL stray field acting on the free layer (FL), a compensation magnet (CM) is inserted below the FL to form a top-pinned MTJ stack without compromising magnetotransport properties. Devices with centered FL switching loops can be obtained after a two-step field setting. The stray field of CM has limited impact on the RL due to the large distance in between, thus keeping the RL's pinning field larger than 150 mT down to devices with 20-nm CD. Finally, current switching is realized in devices with SFM and CM, showing critical current density around 5-8 MA/cm(2) and an averaged thermal stability as high as 50. Thus, the SFM pinning layer design shows great potential in stabilizing top-pinned devices and paves the way for multiple future spintronic applications requiring a top-pinned stack design.

Analogous device parameters in both the parallel (P) and anti-parallel (AP) states ensure a symmetric spin-transfer-torque magnetic random-access memory operation scheme. In this study, however, we observe an increasing asymmetry in the performance metrics with operating temperature of the bottom-pinned perpendicular magnetic tunnel junction (p-MTJ) devices. A temperature-dependent increase in the contribution of the stray field is observed in the tunneling magnetoresistance loop analysis. The switching current for P-to-AP decreases by 30% in the thermally activated switching regime by increasing the temperature from 300 K to 400 K, while it remains similar for AP-to-P. In addition, with the same temperature range, the thermal stability factor for the P state decreases 20% more than that for the AP state. We attribute those observations to the increase in the overcompensation of the stray field from the synthetic anti-ferromagnet structure. Saturation magnetization (MS) of the [Co/Pt]x-based multilayers is much less affected by temperature [MS(400 K)/MS(300 K) = 97%] compared to that of the CoFeB-based multilayers (88%). Such an impact can be more severe during the electrical switching process due to the Joule heating effect. These results suggest that, to understand and to evaluate the performance in a wide range of temperatures, it is crucial to consider the contribution of the entire magnetic components in the p-MTJ stack.

We demonstrate for the first time full-scale integration of top-pinned perpendicular MTJ on 300 mm wafer using CMOS-compatible processes for spin-orbit torque (SOT)-MRAM architectures. We show that 62 nm devices with a W-based SOT underlayer have very large endurance (> 5x10^10), sub-ns switching time of 210 ps, and operate with power as low as 300 pJ.

We investigate the Gilbert damping and the magnetization switching of perpendicularly magnetized FeCoB-based free layers (FLs) embedded in magnetic tunnel junctions adequate for spin-torque-operated magnetic memories. We first study the influence of the boron content in MgO/FeCoB/Ta systems alloys on their Gilbert damping parameter after crystallization annealing. Increasing the boron content from 20% to 30% increases the crystallization temperature, thereby postponing the onset of elemental diffusion within the FL. This reduction of the interdiffusion of the Ta atoms helps maintaining the Gilbert damping at a low level of 0.009 without any penalty on the anisotropy and the magnetotransport properties up to the 400 °C annealing required in CMOS back-end-of-line processing. In addition, we show that dual MgO FLs of composition MgO/FeCoB/Ta/FeCoB/MgO have a substantially lower damping than their MgO/FeCoB/Ta counterparts, reaching damping parameters as low as 0.0039 for a 3 Å thick tantalum spacer. This confirms that the dominant channel of damping is the presence of Ta impurities within the FeCoB alloy. On optimized tunnel junctions, we then study the duration of the switching events induced by spin-transfer torque. We focus on the sub-threshold thermally activated switching in optimal applied field conditions. From the electrical signatures of the switching, we infer that once the nucleation has occurred, the reversal proceeds by a domain wall (DW) sweeping though the device at a few 10 m/s. The smaller the device, the faster its switching. We present an analytical model to account for our findings. The DW velocity is predicted to scale linearly with the current for devices much larger than the wall width. The wall velocity depends on the Bloch DW width, such that the devices with the lowest exchange stiffness will be the ones that host the DWs with the slowest mobilities.

For the first time, we demonstrate, using an atomistic description of a 30nm diameter spin-transfer-torque magnetic random access memories (STT-MRAM), that the difference in mechanical properties of its sub-nanometer layers induces a high compressive strain in the magnetic tunnel junction (MTJ) and leads to a detrimental magnetostrictive effect. Our model explains the issues met in engineering the electrical and magnetic performances in scaled STT-MRAM devices. The resulting high compressive strain built in the stack, particularly in the MgO tunnel barrier (t-MgO), and its associated non-uniform atomic displacements, impacts on the quality of the MTJ interface and leads to strain relieve mechanisms such as surface roughness and adhesion issues. We illustrate that the strain gradient induced by the different materials and their thicknesses in the stacks has a negative impact on the tunnel magneto-resistance (TMR), on the magnetic nucleation process and on the STT-MRAM performance.

We have studied experimentally the nanosecond-scale spin-torque-induced switching in perpendicularly magnetized tunnel junctions.