In this work, we demonstrated 3D sequential complementary field-effect-transistor (CFET) by direct wafer bonding (DWB) technique and a low-temperature process for monolithic 3D(M3D) integration using a high-performance top Ge (110)/<110> channel on bottom Si CMOS. Here, the maximum thermal budget was up to 400°c during the fabrication of top Ge FET, allowing high-performance heterogenous Ge/Si CFET without damage to bottom Si FETs. Furthermore, we systematically investigated the mobility enhancement to channel orientation in thin Ge (110) nanosheet channel pFET. Low effective hole mass along <110> direction on Ge (110), which was calculated by the k$\cdot$p method, provided record high mobility of approximately 400 cm2/V$\cdot$ s (corresponds to 743 cm2/V$\cdot$ s when normalized by footprint) among the reported Ge pFET with similar channel thicknesses at room temperature.
To continue contacted gate pitch scaling, transistor with improved electrostatics, gate stack innovation, and appropriate contact scheme along with improved process control to reduce variability are all indispensable factors. As gate pitch scales into the sub-50nm regime, electrostatics of FinFET architecture, spacer material, and traditional contact scheme all approach their engineering limits. Here we report a leading-edge CMOS technology developed at 45nm contacted gate pitch that successfully incorporates optimized fin profile, low-k spacer and self-aligned contact scheme. The process robustness is validated by a logic test chip with >3.5 billion transistor gate count and fully functioning 256Mb HC/HD SRAM macros. The demonstrated high-density SRAM cell size of $0.0199 \mu \mathrm{m}^{2}$ is the smallest reported to date.
Homomorphic encryption (HE) is an encryption technology of which encryption and decryption process can be summarized as polynomials modulo multiplication computing with noise. In this paper, HE is firstly implemented on resistive random-access memory (RRAM) arrays, which are utilized as both matrix-vector multiplication (MVM) units and true random number generators (TRNG). Both high stability and good randomness are achieved for MVM and TRNG, respectively, by using different forming schemes, so that two distinct functions can be realized using the same device. Furthermore, the encryption-decryption process for privacy-preserving cloud computing is experimentally implemented on a hardware system with eight 144Kb RRAM arrays. For the whole RRAM array-based encryption-decryption process, small accuracy losses of 0.73% (for SVM) and 1.9% (for CNN) are achieved. This is the first demonstration of encryption computing acceleration with emerging device technology.
A complete picture of the dynamics of the ferroelectric oxide/metal interface is presented, which unifies the main reliability issues, field cycling endurance, and retention for HfO 2 –based films in ferroelectric random-access memory. Together with a novel retention interpretation, the ferroelectric interface is established as the key component for pioneering HfO 2 -based ferroelectrics for commercial memories.
The recent huge success of AI requires the development of dedicated H/W solutions for massive basic arithmetic operations – multiply and accumulation (MAC). Inmemory computing is one of the most progressive attempts in AI acceleration. The key embodiment of in-memory computing is the crossbar array of conductive memories. The crossbar array stores neural net weights in situ and performs MAC operations in an analog manner to significantly reduce power consumption. Here we innovate device and circuit solutions to develop the first MRAM crossbar array using Samsung 28-nm embedded MRAM CMOS technology.
We report the first experimental demonstration of a vertical superjunction device in GaN. P-type nickel oxide (NiO) is sputtered conformally in $6 \mu \mathrm{m}$ deep n-GaN trenches. Sputter recipe is tuned to enable $10 ^{17}$ cm $^{-3}$ level acceptor concentration in NiO, easing its charge balance with the $9 \times 10 ^{16}$ cm $^{-3}$ doped n-GaN. Vertical GaN superjunction p-n diodes (SJ-PNDs) are fabricated on both native GaN and low-cost sapphire substrates. GaN SJ-PNDs on GaN and sapphire both show a breakdown voltage $( BV)$ of 1100 V, being at least 900 V higher than their 1-D PND counterparts. The differential specific on-resistance $( R_{ON,SP})$ of the two SJ-PNDs are both $0.3 \mathrm{m}\Omega \cdot$ cm 2 , with the drift region resistance $( R_{DR,SP})$ extracted to be $0.15 \mathrm{m}\Omega \cdot$ cm 2 . The $R_{ON,SP} \sim BV$ trade-off is among the best in GaN-on-GaN diodes and sets a new record for vertical GaN devices on foreign substrates. The $R_{DR,SP} \sim BV$ trade-off exceeds the 1-D GaN limit, fulfilling the superjunction functionality in GaN.
We report on Snapdragon ®888 mobile platform. It is the first integrated 5G modem SoC Flagship Platform for premium tier smartphones using 5nm EUV FinFET technology. It exhibits >20% CPU performance gain over its predecessor Snapdragon 865 thanks to a new design architecture and multiple process improvements. Manufacturability was ready in time for mass production start. Product Quality was significantly improved with key process optimization and very low-voltage memory repair enablement. Low voltage operation and low power consumption are also achieved with further Design-Technology-Co-Optimization (DTCO), enabling premium-tier performance experience with integrated 5G and AI mobile SOC platform.
In this work, a 14-nm-node Replacement Metal Gate (RMG or “Gate Last”) high-k Last FinFET flow, compatible with the high thermal budget required during a DRAM fabrication process is demonstrated for the first time, with proven functionality of SRAM and Ring Oscillators. An extensive analysis is conducted for the assessment and optimization of the nMOS gate stack. A thermally stable nMOS gate stack featuring Lanthanum (La)-dipole and TiN/TiAl/TiN Work Function Metals (WFMs) is proposed to achieve sub 0.2 V nMOS threshold voltage $(V_{t})$.
Here we present a hybrid computing-in-memory (CIM) architecture, named M3D-CCP, by monolithically 3D integration of Si CMOS logic layer, RRAM-based CIM layer and processing-near-memory (PNM) layer with CNT/IGZO-based complementary field-effect transistor (CFET). The Si-CMOS layer was fabricated using a standard 130 nm process and served as control logic. The CIM layer consisted of ITIR arrays with analog resistive random-access memory (RRAM) for matrix-vector multiplication (MVM) operations in neural networks. The CFET-based PNM layer was fabricated with carbon nanotube FET (CNT-FET) and InGaZn$\text{O}_{\text{x}}$ FET (IGZO-FET) for caching and processing data between layers of neural networks. Both the CIM and PNM layers were fabricated using a low-temperature ($\leq$300 °c) backend-of-the-line (BEOL) process. The structural integrity and proper function of each layer were verified. Furthermore, an image super-resolution task was implemented using the fabricated M3D-CCP chip, achieving GPU-equivalent performance on the DVI2K dataset with $149\times$ lower energy consumption. Our work demonstrates the feasibility and great potential of such hybrid CIM architecture for data-abundant applications such as artificial intelligence (AI) and high-performance computing (HPC).
Nanopore technology has augmented DNA sequencing, and nascent nanopore-based technology breakthroughs may lead to major steps forward in large-scale molecular analysis (omics) and DNA digital data storage. A major weakness of current nanopore technologies is the requisite recording of pico-to nanoampere ionic currents. Such low currents limit recording bandwidth in large integrated arrays and impose a limit on how quickly a detectable molecule can cross, or translocate the pore. The Nanopore Field Effect Transistor (NPFET) is a nanopore surrounded by a nanoscale field-effect transistor. The field-effect transistor senses single molecules translocating through the pore relying on much larger microampere currents. The NPFET potentially offers higher bandwidths in large integrated arrays and the breaking of the nanopore translocation speed limit. Moreover, because individual electrolyte contacts are not required for NPFETs they are more easily integrated into large arrays than nanopores. NPFETs may lead to major strides in high throughput reading of molecularly encoded information. We will introduce and elaborate on nanopore FET technology research for omics and DNA data storage and we will propose a scaling roadmap that aims to incrementally boost NPFET molecular read throughput.
To efficiently process vision data at sensor terminals, we demonstrate a 2T2RlC pixel cell for in-sensor spike neural network (SNN) that can sense and process vision informations with event-driven characteristics. Compared with conventional event-based cameras with Si photodiode that requires complicated CMOS circuit design for high dynamic range (120dB), our2T2RlC cell with two-dimensioinal MoS 2 phototransistors exhibits inherently high dynamic range (140 dB), thus greatly simplifying event-driven sensor circuit design. The photoresponvity of MoS 2 phototransistors ranges from 1$0^{-4}$ to 10 4 mA/W by modulating gate voltages, emulating the synaptic weights in a neural network. Based on this sensor, we construct an in-sensor SNN and successfully perform a lane keeping task in an event-driven manner. Instead of sensing and generating the spike signals of all pixels, our design saves 97% data by only processing the local pixel with the change of light intensity. When an event is triggered (light intensity changes from 1.6 to 5.1 mWc$\mathrm{m}^{-2}$), each pixel realizes event-based sensing and processing simultaneously with ultralow power consumption (160nW), showing the potential for energy-efficient edge intelligence.
In this work, CMOS-compatible ferroelectric (FE) $\mathrm{H}\mathrm{f}\mathrm{O}_{2}$ capacitor based processing-in-sensor (PIS) hardware is proposed and experimentally demonstrated for the first time, realizing zero-power sense and inference with in-situ motion detection and four-quarter multilevel multiply-accumulation (MAC). By utilizing the intrinsic pyroelectric effect and the multi-domain features of F$\mathrm{E}-\mathrm{H}\mathrm{f}\mathrm{O}_{2}$, the proposed non-volatile PIS device can experimentally implement local multiplication of sensing input signal and polarization-modulated signed weight by only one FE capacitor, without the need of sensing power or extra peripheral differential circuits for motion detection, along with the advantages of low operation voltage (2V), high endurance (10 14 cycles), long retention (10 years) and good consistency. Besides, the optimized fabricated FE- $\mathrm{H}\mathrm{f}\mathrm{O}_{2}$ PIS device also exhibits the record highest pyroelectric sensitivity among $\mathrm{F}\mathrm{E}-\mathrm{H}\mathrm{f}\mathrm{O}_{2}$ materials. Furthermore, the infrared (IR) response of the proposed FE-PIS array is also experimentally demonstrated, enabling multilevel signed MAC with high linearity for IR motion detection. Based on proposed FE-PIS design, motion pattern recognition and further data compression tasks with high accuracy (99%) are realized, showing its great potential for edge AI.
Micro-structured monolithic CMOS devices enable the integration of dense microelectrode arrays and on-chip circuits for low-power implantable brain interfaces with single neuron spatiotemporal resolution. Here, we demonstrate the scalability of SiNAPS CMOS-probe technology with respect to different probe layouts, array sizes and shank dimensions down to microwire size ranges.
We propose a novel ab inito defect modeling framework for devices based on two-dimensional (2-D) transition-metal dichalcogenide (TMDC) monolayers. The so-called projected (p)- GW method is combined with density functional theory and incorporated into the non-equilibrium Green’s function equations to efficiently and accurately investigate the influence of various defect types on the characteristics of 2-D field-effect transistors. Through quasi-particle correlated defect-level modeling, we show that one single defect located inside the channel under the gate is a main source to block the current flow, thus leading to a large performance degradation. Our variability study also confirms that defects inside transistors based on 2-D TMDC monolayers induce a significant threshold voltage shift and ON-state current variation.
Hardware accelerators that exploit analog in-memory computing offer an energy-efficient edge deployment solution for machine learning algorithms. We give an overview of the device requirements and hardware-software co-design principles for these systems to achieve efficient and accurate deep neural network (DNN) inference. We designed and fabricated a 40nm test chip with a $1024 \times 1024$ SONOS (siliconoxide-nitride-oxide-silicon) charge trapping memory array for DNN inference. Operating the SONOS memory in the subthreshold regime suppresses the effects of device variability on algorithm accuracy. We experimentally demonstrate accurate DNN inference using the test chip on CIFAR-100 image classification and project a chip-level efficiency of >50 TOPS/W for the SONOS inference accelerator, a $10 \times$ advantage over state-of-the-art digital inference accelerators.
The slowing down of Moore’s Law has created an exciting new era of electronics, leading to the emergence of various types of CMOS+X devices and architectures. Here, we present the first experimental demonstration of a probabilistic computer where a stochastic magnetic tunnel junction (sMTJ) drives a powerful CMOS-based field programmable gate array (FPGA) in a heterogeneous compute fabric. We use our machine to experimentally evaluate the simulated quantum annealing (SQA) algorithm, known to closely mimic the behavior of D-Wave’s quantum annealers which implement the transverse field Ising model (TFIM). Our machine matches the exact solution of the TFIM where p-bits in the FPGA are asynchronously driven by the stochastic dynamics of a magnetic tunnel junction. To compare the performance of SQA against classical annealing (CA) in hard combinatorial optimization at large scale, we also design a fully digital emulator of our asynchronous architecture in the FPGA. Our digital system uses 7,085 p-bits to factor up to 26-bit integers and is about 10X faster than optimized Tensor (TPU) and Graphics Processing Units (GPU) at lower power. Surprisingly, we find that the additional replica networks necessary for SQA do not lead to appreciably better performance over an optimized CA that is using the same computational resources. The systematic evaluation of the SQA algorithm we present will be relevant for other types of accelerators, such as photonic or electronic Ising machines and the integrated scaling of our CMOS + sMTJ architecture could lead to orders of magnitude further improvements over TPU and GPUs, according to experimentally-validated projections.
Conventional X-ray imaging architectures feature data redundancy and hardware consumption due to the separated sensory terminal and computing units. In-sensor computing architectures is promising to overcome such drawbacks. However, its realization in X-ray range remains elusive. We propose ion distribution induced reconfigurable mechanism, and demonstrate the first X-ray band in-sensor computing array based on Pb-free perovskite. Redistribution of Br – ion in perovskite induces the switching of PN and NP modes under electrical pooling. X-ray detection sensitivity can be switched between two stable self-power sensing modes with 4373±298 and -7804±429 $\mu \mathrm{CGy}_{\mathrm{a}\mathrm{i}\mathrm{r}}{}^{-1} \mathrm{cm}^{-2}$ respectively, which are superior than that of commercial a-Se detectors $(20\mu \mathrm{C}\mathrm{G}\mathrm{y}_{\mathrm{a}\mathrm{i}\mathrm{r}}{}^{-1}\mathrm{c}\mathrm{m}^{-2})$. Both modes exhibit low detection limit of 48.4 $\mathrm{n}\mathrm{G}\mathrm{y}_{\mathrm{a}\mathrm{i}\mathrm{r}}\mathrm{s}^{-1}$, which is two orders lower than typical medical dose rate of 5.5 $\mu \mathrm{G}\mathrm{y}_{\mathrm{a}\mathrm{i}\mathrm{r}}\mathrm{s}^{-1}$. The perovskite array sensors can integrate with thin film transistors (TFTs) with low-temperature (80oC) process with good uniformity. An in-sensor computing algorithm of attention mechanism is performed on array sensors for chest X-ray images COVID-19 recognition, which enables an accuracy improvement up to 98.2%. Our results can pave the way for future intelligent X-ray imaging.
Despite the great promises of resistive random-access memory (ReRAM) for fast, low-power in memory computing, the models deployed on ReRAM crossbars suffer from accuracy loss, due to poor yield, inaccurate switching and high noise. In this paper, we report a forming-free bulk ReRAM (b-ReRAM) cell that can be programmed up to 128 levels between 400nA $(4\mu \mathrm{S})$ and $4\mu A (40\mu S)$. The device operates by continuous modulation of bulk oxygen vacancies, therefore exhibiting favorable characteristics including forming-free operation, analog switching, low noise and low operating currents [1], [2]. The multilayer ReRAM stack is deposited using a specially built 300mm deposition system that features a clustered sequence of Physical Vapor Deposition (PVD) and Atomic Layer Deposition (ALD), leading to high wafer-level yield and uniformity. High programming accuracy can be achieved over 25k b-ReRAM devices across 15 dies. A fully integrated system on chip (SoC) with BEOL-integrated b-ReRAM arrays is built with 65nm CMOS technology, and keyword spotting (KWS) is demonstrated with accuracy equivalent to the software quantized model and high energy efficiency at 98.5 TOPS/W. Moreover, we evaluate the performance of the bitcell for large neural network (NN) applications in a custom hardware-aware simulation platform and show that software comparable accuracy can be achieved. This work for the first-time reports that high yield and high programming accuracy can be achieved with b-ReRAM at the wafer-level scale and demonstrates that superior analog behavior enables the mapping of NN models onto the ReRAM-based SoC prototype with no accuracy loss and high energy efficiency.
The paper presents the first comprehensive analysis of the electrical contact topologies to two-dimensional (2D) transition metal dichalcogenide (TMD) semiconducting materials by employing ab-initio density functional theory (DFT) and non-equilibrium Green’s function (NEGF) formalisms. Using Landauer’s equations, comprehensive numerical models for contact resistance (R C ) of these contact configurations have been derived and subsequently extended to develop the first closed-form expressions for contact resistance to 2D materials (2DM) in these configurations. The comprehensive modeling framework, which includes boundary and interface scatterings, Fermi level pinning (FLP) through metal induced gap states (MIGS), terminated edge states, and surface reconstructions due to interface bonding, the effect of FLP quenching through the presence of a van der Waals (vdW) gap, and the physics of carrier transport across such an interface, is intended for designing 2D FETs with minimal R C and extracting from experiments the accurate Schottky barrier (SB) height to model realistic 2D-FET device/circuit performance. Hybrid contacts with sufficient (~2 nm) metal-2DM overlap are found to be optimal, and carrier (doping) concentrations and SB height needed for satisfying IRDS requirements have been identified.
We investigate several options for metal contacts to monolayer 2D semiconductors with an in-house developed, ab-initio transport methodology. We identify an optimum separation between the metal and the semiconductor resulting in minimum contact resistance $(R_{\mathrm{C}})$. Such a minimum $R_{\mathrm{C}}$ is fundamentally related to the trade-off between Schottky barrier height and tunneling barrier width. We examine quantitatively the effects of buffer layers and report, for the first time, ab-initio R calculations for the $\mathrm{b}\mathrm{i}\mathrm{s}\mathrm{m}\mathrm{u}\mathrm{t}\mathrm{h}-\mathrm{M}\mathrm{o}\mathrm{S}_{2}$ system, comprising the influence of the inelastic electron-phonon interaction. Finally, we investigate $\mathrm{A}\mathrm{u}-\mathrm{W}\mathrm{S}\mathrm{e}_{2}$ as a material system for a low $R_{\mathrm{C}}$ -type contact.
