The introduction of emerging technologies into existing manufacturing facilities is not necessarily encouraged by the people responsible for the output of the facilities. Any "new" technology carries risks and people responsible for delivering manufactured products are, by nature, risk-adverse. This paper demonstrates the advantage of evaluating the impact of attempting to introduce a new technology into an existing facility before actually attempting the introduction. The first part of the analysis examines the impact on the total product delivery for a comparable volume of two facilities, one with the traditional processes and one with the new process replacing existing ones. Based on these results, a conclusion can be reached if there are sufficient benefits to consider pursuing the development and introduction of the new techniques. An example is employed that evaluates the introduction of nano-imprint.

The Journal of Micro/Nanopatterning, Materials, and Metrology (JM3) publishes peer-reviewed papers on the core enabling technologies that address the patterning needs of the electronics industry.

This paper describes the status of 157-nm lithography in mid 2004. With the rapid rise of 193-nm immersion from a potential concept in early 2002 at SPIE, through its development,to scheduled delivery of early production tools in late 2004 and early 2005, 157-nm lithography has taken a backseat in the development of optical lithographic technology. While significant challenges were conquered during the 2000 through 2002 period, the development was too slow to prevent 157-nm from being eclipsed by 193-nm immersion. This work reviews the challenges that were identified and conquered during the development of 157-nm lithography. The jury is still out on potential application to production lithography, although the main development effort has been seriously scaled back. There are still issues that remain to be solved before the technology could evolve into a full manufacturing system. The answer to the question of whether it will evolve or not is left to the future to answer. (c) 2005 Society of Photo-Optical Instrumentation Engineers.

Abstract Surface mount assembly (SMA) is the description of a technology that incorporates the electrical and mechanical of components to printed wiring boards (PWBs) or a similar type of circuit substrate. The term surface mount comes from the methodology of attaching the components. Many categories of packages can be employed in surface mount assembly. They can be identified into two categories: leadless devices and leaded chip carriers.

Mask cleaning has been a significant challenge. Advanced PhotoMasks have proven to be even more difficult. The experimental work on 157nm systems uncovered an issue of particle growth under the pellicle. Since the mask blank had a different composition from existing production mask blanks, there was not a concern about current production impact. Investigations were started after a few incidents occurred on 193nm masks. The investigations demonstrated that the masks have a consistent family of contaminants that are on all chrome absorber masks. The initial work provided clues to the nature of the particle growth and some indication of the potential sources. The issues seemed to evolve from the total system and not a single contaminant source. Currently, hard defects due to particle growth under the pellicle occur industry wide. This paper will provide the methodology employed for a recent cleaning evaluation and identify some of the culprits that cause particle growth. The issue has grown to a major problem and needs to be quickly addressed.

Chrome-based absorbers have been the mainstay of the photomask industry for three decades. While chrome is attractive because of its durability and opacity, it conversely poses challenges for etch and repair. Due to large capital investments, any new absorber must be designed to work with existing scanners, mask writers, and mask inspection tools. Furthermore changing absorber materials may not improve defect control in mask blank fabrication, which is a paramount concern in blank fabrication. Consequently, blank manufacturers are reluctant to change from chrome. In terms of return on investment (ROI), the only driver to switch technologies is achieving higher mask and wafer yields. This is a reasonable assumption as both etch and repair tool suppliers believe a non-chrome material like tantalum (Ta) compounds would significantly improve their capabilities with known technologies. A high level estimate shows that with even aggressive improvement assumptions, a 100% conversion from chrome does not save money. Based on the current International SEMATECH (ISMT) cost of ownership (COO) model and improved yields for critical dimension (CD) and defects, a case can be made for converting at and below 100 nm ground rules. An industry wide conversion from chrome to a non-chrome absorber is estimated to cost $100M. By contrast, blank suppliers are reportedly spending "multiple" millions of dollars to improve chrome per year. A widespread concern is whether binary optical masks have enough life left to provide sufficient ROI. Optical lithography will continue to be of use in the foreseeable future. Even as leading-edge production moves to new technology, the main manufacturing volumes will continue to create significant demand for masks for 100 nm to 45 nm for many years. With the industry currently pushing extreme ultraviolet lithography (EUVL), the best situation would be for EUVL and optical lithography to choose the same absorber material. This creates a winning situation for the industry independent of EUVL implementation timing. Today Ta-based films are a reasonable choice.

The technology acceleration of the ITRS Roadmap has many implications on both the semiconductor supplier community and the manufacturers. This work examines the impact of technology acceleration on the suppliers, the manufacturers of tools, materials, and masks. From an Industry perspective, the development and product life cycle are examined with respect to the resources required and the return on investment. Historical information is available regarding the length of time required to develop a manufacturing worthy product. Resource requirement estimates are available, so it is possible to develop an investment curve for product development. Similarly, estimates of total product sales provide the basis of the investment recovery scenario. From these evaluations, the Industry return on investment can be projected. It is possible to evaluate the impact of changes in technology on suppliers as the industry moved from 248nm to 193nm.

There has been a proliferation of examples of mask cost projections for future ITRS nodes and various technologies. This paper reviews the methodology developed at SEMATECH to insure that projected mask costs reflect the geometries being planned. A detailed description provides the development of the mask manufacturing process and develops a projected cost.

The technology acceleration of the ITRS Roadmap has many implications on both the semiconductor supplier community and the manufacturers. This work examines the impact of technology acceleration on the manufacturers and the resultant supplier impact. This work begins with an overview of the forces in the industry that are driving the acceleration. Providing an analysis of the drive behind the acceleration, the impact on total production is developed. This acceleration results in more functionality per unit area in a shorter time frame. Based on a constant growth of devices, the technology acceleration reduces the requirements for manufacturing capacity increases. This fact has a direct impact on the supplier community. An additional factor is introduced, which is time to market. An analysis of the impact of "winning" the time to market race provides insight into a key industry driver. This work provides an improved understanding of the market forces that drive the semiconductor industry.

International SEMATECH has been a focal point for the 157nm effort worldwide. Since beginning the program in 1998, ISMT has provided forums for information dissemination ona semi- annual basis. The ability to develop a consensus to identify the most pressing critical issues has permitted the industry to develop this technology more rapidly than any other has been developed. There are still many issues that remain, but even the unexpected have been addressed and solutions put in place. There is a lesson to be learned that a concerted effort involving the entire industry can provide solutions to even the most difficult problems. The development is not completed, but the end is in sight. 157 nm lithography will be developed faster than any other technology due to the entire industry working in concert.

This paper addresses an approach to the discovery of scientific knowledge. Swanson showed that it is possible to obtain new or undiscovered public knowledge by evaluating existing published information from technically linked by bibliographically isolated publications. With the availability of data mining and text mining tools, the ability to duplicate Swanson's results would appear to be promising. This paper will present the results of experiments that address knowledge acquisition from a selected set of technical documents by domain experts. Based an these results, conclusions are drawn on the future direction of research.

We review progress on a project to evaluate prospective operations in a semiconductor wafer fab that employs next generation, proximity X-ray lithography to pattern the critical dimensions of computer chips. A simulation model is developed that captures the processing of wafers through an X-ray lithography cell using a synchrotron as the source of exposure radiation. The model incorporates the best current information on unit-cell design and processing times and implements a range of events that interrupt the flow of wafers processing on the cell. Performance measures estimated from the simulation include the weekly throughput for the cell and the frequency of SEMI E-10 equipment states for the corresponding exposure tool. Simulation experiments are conducted to compare the performance of a cell fabricating 200 mm wafers with that of a cell fabricating 300 mm wafers, for each of three different chip sizes. Results illustrate the anticipated dependence of average wafer throughput on wafer size and assumptions regarding the number of chips per wafer, with a maximum of approximately 3400 wafers/week for 200 mm wafers with 25/spl times/25 mm field size. Ignoring wafer-sort losses, however, a maximum throughput of approximately 410,000 chips/week is realized for 300 mm wafers with 11/spl times/22 mm fields. Remarkably, the distribution of equipment states remains relatively unchanged across simulation experiments.

Bulk (or global) heating of photomasks due to e-beam energy deposition during patterning causes thermal expansion of the mask substrate and leads to pattern placement errors. Finite element calculations were performed to simulate the in-plane distortions (IPD) due to the single pass writing of a 6 in. x 6 in. optical reticle. Comparison studies were performed to identify the effects of material properties (such as thermal conductivity and the coefficient of thermal expansion) when patterning SiO2 and CaF2 substrates. Final IPD maps illustrate that thermal distortions of the CaF2 will need to be controlled in order to satisfy increasingly stringent error budgets.

This paper considers the development of the design for manufacture efforts in electronics manufacturing. While there were many distinct efforts in the 1980s, only one, the manufacturability rating system addressed the needs of the electronics manufacturing community. While the methodology was successfully applied within the larger manufacturing companies, the effort was not able to be sustained. Today's environment demands a complete approach to solving the challenges in competing in a global market. The semiconductor industry of 1995 has demonstrated the need to develop a systematic approach to a total solution. Solutions to this identified need in semiconductors can be the basis of solutions for the electronics industry in general. The designs of semiconductor devices relies heavily on automated functions to provide the increasing complexity of circuits. Somewhere about the early 1980s it became impossible to attempt a semiconductor design without automated tools as the number of transistors increased over 10000 on a single device. The capability of the manufacturing process (circuit complexity) in semiconductors is increasing at the rate of almost 60% per year. In comparison, the design tool productivity has been increasing at the rate of about 20% per year. The major challenge is this gap between manufacturing capability and design tool capability that will result in a problem for the industry if the needs are not addressed. This paper considers the enhancements that need to be developed in order to solve this challenge.