We present an efficient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations consist of adding redundant connections or gates so as to reduce the switching activity. Simple and efficient procedures, based on logic implication, for identifying the sources and targets of the redundant connections are presented. Additionally, procedures that permit the designer to trade-off power and delay after the transformations are described. Results of experiments on the MCNC benchmark circuits are given. The results indicate that significant reduction of the switching activities of a CMOS combinational circuit can be achieved with a very low area overhead and low computational cost.

Physical properties of both electron trapping and detrapping are identified to influence the degradation behavior of p-MOS transistors. Focusing on electron trapping first, we find as a decisive feature a spatially growing region of filled traps in the vicinity of the drain. Due to an exponential decrease of the electron injection current as a function of distance to the drain, its length grows logarithmically over time resulting in a logarithmic time dependence of the degradation. The logarithmic growth of this region is proven by means of charge-pumping experiments, whereas the logarithmic time dependence of the degradation itself is readily visible in the transistor current. Including electron-detrapping, the model permits a consistent description of both time- and bias-dependence of the degradation thereby leading to an improved expression for the lifetime of p-MOS transistors

The relationship between hot-carrier degradation in MOSFETs and CMOS inverters is studied. It is found that the device degradation characterized as the widely used bias points correlates poorly with the inverter degradation. The use of new bias points that are more meaningful for circuit performance is proposed. A simple equation for calculating the degradation of the propagation delay is developed.<>

The degradation of p-MOS transistors is shown to proceed logarithmically in time. A simple, analytic degradation model is proposed that fully accounts for this observation. The logarithmic time dependence originates from the logarithmic growth of a region of filled traps from the drain junction towards the source. On this basis, a reliable lifetime extrapolation is performed.<>

This paper presents a new model for understanding the saturated time dependence of hot-carrier degradation in LDD nMOSFETs. The peak of the lateral field, and thus the zone of high injection current, moves into the LDD region where generated interface states are of almost no influence on the MOSFET I(V)-characteristics.