Microfluidics is a rapidly growing field that aims to simplify complex analytical procedures by moving them to small-scale devices. A particularly interesting application of microfluidics are so-called Organs-on-Chips, i.e., microfluidic devices that mimic the structure and function of human organs and, therefore, allow studying the effects of drugs and diseases. Recent recognition of the need for standardization in this domain has led to the generation and uptake of new ISO standards—providing the basis of modular and reusable microfluidic building blocks that allow for various organ-on-chip setups. However, designing these building blocks, especially so-called routing blocks that interconnect pumps, cell cultures, and other modules is a cumbersome, repetitive task that is still conducted manually. In this work, we propose a design and routing method that significantly simplifies the design of such routing blocks by fully automating the process of interconnecting components of a microfluidic chip. The evaluation of physical, fabricated routing blocks that were designed using the proposed method showcases its feasibility in real-world applications and its potential to reduce design effort and time significantly. In order to make the work accessible to the microfluidic community, we provide implementations of the resulting methods in the form of a user-friendly, interactive online tool, provided as part of the Munich Microfluidic Toolkit (MMFT).
Homomorphic Encryption (HE) provides strong privacy guarantees by enabling computation directly on encrypted data, but at the cost of substantial computational overhead. Despite recent advances in algorithms and hardware, a gap remains between theoretical feasibility and practical deployment. To close this gap, we advocate a new encrypted computing paradigm that integrates application-level insights with ciphertext encoding to maximize Single-Instruction-Multiple-Data (SIMD) efficiency. Specifically, it comprises (1) pattern-aware encoding along the dominant reduction axes to reduce rotations, (2) Interleaved Assembling to re-densify ciphertexts after dimension reductions, and (3) encryption-aware Rot-structural pruning to exploit weight sparsity in accelerating encrypted neural network computation. On GPUs, it achieves speedups of up to 191× (Cora), 96× (Citeseer), 27× (Pubmed), on graph neural networks (GNNs) and 7.8–27.6× (MNIST and CIFAR-10) on convolutional neural networks (CNNs) such as LeNet, VGG5, ResNet20, all without accuracy loss. We conclude with an outlook on extending this design to large language models and beyond.
Advancing technology nodes have significantly increased the complexity of transistor sizing in analog circuit design. Although artificial intelligence (AI) techniques show potential, their lack of integrated domain expertise often leads to slow convergence in practical applications. We propose ASTRA (Automatic Sizing of Transistors with Reasoning Agents), a novel optimization framework that implements the Model Context Protocol (MCP) to create structured reasoning pathways between Large Language Models (LLMs), domain knowledge bases, and Bayesian Optimization (BO). ASTRA introduces a two-stage process: first, MCP-guided design initialization that leverages Retrieval-Augmented Generation (RAG) to quickly identify feasible regions using gm/ID methodology; and second, BO-based optimization focused on critical transistors, identified through LLM reasoning with data-driven validation. A key innovation of ASTRA is its ability to seamlessly integrate with and enhance virtually any existing transistor sizing algorithm at minimal additional cost. Unlike purely data-driven or black-box LLM approaches, ASTRA maintains traceable decision processes that can be verified and refined. Evaluated on three real-world analog circuits, ASTRA enhances multiple classical optimization methods, achieving up to 4.35× fewer simulation iterations and 2.36× performance improvements, demonstrating its effectiveness as a general open-source framework for advancing analog circuit sizing. 1
Spiking neural networks (SNNs) have emerged as a promising paradigm for energy-efficient neural computation, offering advantages over artificial neural networks (ANNs) by using sparse spike activations. Among SNN models, spiking transformers have shown great potential in achieving high accuracy while maintaining low energy consumption, making them ideal for resource-constrained applications. However, a significant challenge in accelerating Spiking Transformers lies in managing the inherent unstructured sparsity in spike activations. This sparsity introduces substantial hardware overhead, limiting the efficiency of existing accelerators.To address these challenges, we propose SPARTA, an algorithm-hardware co-optimization framework designed specifically for spiking transformers. SPARTA utilizes a spike-aware dynamic token skipping algorithm, which applies reinforcement learning to selectively skip less informative tokens, achieving structured token-level sparsity in both spatial and temporal domains. Additionally, we introduce the spike-aware token prediction algorithm to predict and eliminate inactive tokens, further improving efficiency. Meanwhile, we present a dedicated heterogeneous ReRAM-based Compute-in-Memory (CIM) hardware architecture tailored to support token-level sparsity, which integrates a ReRAM analog CIM engine for linear layer and a token-spike fusion engine for optimized token routing and spike attention. Experimental results show that SPARTA achieves up to 543.1× and 10.2× speedup with 308.0× and 5.2× energy efficiency improvement compared to GPU and the state-of-the-art SNN accelerator "COMPASS", while preserving high model accuracy.
Dynamic programming (DP) plays a crucial role as the backbone of many core optimization algorithms across the physical design flow, including placement, clock tree synthesis, and routing. However, DP methods with quadratic or higher time complexities often face scalability challenges in large-scale designs. In this work, we propose a novel GPU-accelerated DP technique that can be broadly adaptable to various DP-based algorithms. As a case study, we present a GPU-accelerated detailed placement framework targeting mixed-cell-height designs, built upon an optimal DP formulation. By leveraging the massive parallelism of modern GPUs and incorporating advanced cost accumulation strategies, our approach consistently delivers optimal placement solutions while achieving an average runtime reduction of 96.6% and peak speedups exceeding 1600×. This work demonstrates the potential of GPU acceleration not only to overcome runtime bottlenecks but also to enhance design quality in advanced physical design tasks.
As signal frequency increases, signal integrity, a measure of how well a signal is transferred from one component to another, becomes critical in modern electronic products. Thorough signal integrity analysis is essential in design process and S-parameters are often used to model electromagnetic characteristics of a channel such as PCB traces. However, numerous iterations are inevitable due to design changes in components of a product such as different placement on PCBs. Traditional approaches to S-parameter extraction rely on computationally expensive electromagnetic simulations, becoming a bottleneck in the design process. To tackle this issue, we present PCBFormer, a novel deep learning framework that predicts S-parameters of PCBs with high accuracy and efficiency. Our framework effectively captures multiple traces’ electromagnetic interactions across multiple layers in 3D PCB structure, taking each layer’s properties into account. For realistic PCB examples with 10 traces and 25 layers, PCBFormer achieves 0.86 R2 score across 210 S-parameters and DC to 1GHz frequency range.
Heavily constrained edge-side tasks necessitate AI chips with low power consumption, low latency, and low cost. In recent years, digital compute-in-memory (CIM) has emerged as a promising solution to enhance energy efficiency and throughput density. However, digital CIM still faces various challenges: significant power and area overhead from multiplication, difficulty in exploiting fine-grained sparsity, and throughput degradation associated with bit-serial architecture. In this work, we propose Adder-DCIM: an efficient parallel bit-flexible DCIM accelerator joint model compression framework for AdderNet inference, in which the key contributions are: 1) a CIM-friendly model compression framework that includes operator decomposition, lossless fine-grained sparsity, and Kullback-Leibler-divergence(KLD)-based Cin-wise mixed-precision quantization; 2) a synchronous parallel DCIM architecture for throughput improvement with mix-precision quantization; 3) a bit-flexible minimal selector circuit for efficient mixed-precision computation. The experimental results demonstrate that under a 28-nm process, the proposed Adder-DCIM achieves a peak energy efficiency of 134 TOPS/W and a peak throughput density of 6.49 TOPS/mm2 at INT8. When running ResNet20 on CIFAR10 and ResNet50 on ImageNet, the proposed Adder-DCIM achieves 255 TOPS/W@4.2bit and 243 TOPS/W@4.4bit with only a slight decrease in accuracy by 0.34% and 0.7%, respectively. Compared to multiply-based DCIM, Adder-DCIM improves energy efficiency × throughput density metrics by 20.7× for ResNet50 inference.
Exponential integrator (EI) methods have been a promising alternative to backward differentiation formulas (BDF) for transient circuit simulation. However, application of EI to generic nonlinear circuits has achieved only limited success so far, due to numerical instability and difficulty in combining with Newton iterations. In this work, we propose a new nonlinear EI framework, EI-TR, with a novel implicit regularization scheme and a truncated rational (TR) approximation for the treatment of nonlinear functions. The former employs a smart eigenvalue modification to avoid the system partition in the SOTA EI-NK that may induce numerical instability in nonlinear system partitioning. The latter decouples the solutions of the linear and nonlinear systems and reduces the three-layer nested iteration in EI-NK to one single Newton loop similar to conventional BDF, thereby significantly enhancing the performance and robustness of EI for generic nonlinear circuits. Numerical results demonstrate that EI-TR reduces Newton iterations by 3× compared to EI-NK and achieves 6.5x larger time steps than traditional trapezoidal methods.
Hardware generation frameworks (HGFs) leverage high-level descriptions to introduce agile methods into hardware design. However, HGFs still rely on traditional RTL verification workflows, limiting design-verification iteration efficiency. This paper presents ComoPy, an HGF supporting host language native simulation and debugging, introducing software debugging techniques to hardware verification. The framework enables fine-grained tracing and breakpoints directly on HDL source lines, and implements software-style hot-reloading for incremental debug-fix iterations. Furthermore, it supports switching between fast low-level RTL simulation and high-level HDL execution. Case studies on the Sodor-clone processor and a database accelerator featuring systolic array show timely debugging responses, with only a 6% performance loss compared to Verilator simulation.
In-Sensor Computing (ISC) systems integrate sensing and computing units within a single device, enabling low-latency, energy-efficient applications through direct analog-to-feature conversion. However, the intrinsic tight coupling between sensing and computational components introduces significant security vulnerabilities. These arise particularly in scenarios where adversaries have a good understanding of the analog computation mechanisms and could tamper with the ISC device, potentially allowing for manipulation, inference, or extraction of sensitive data. This work introduces exploitable backdoors in ISC that encode the output of the analog computation unit to create covert channels. Through theoretical modeling and empirical case studies, we investigate two ISC-specific covert channels: a logic covert channel and a frequency covert channel. These channels are established by deliberately manipulating the analog computation unit co-integrated with sensing materials on a shared substrate, thereby enabling adversaries to exfiltrate sensitive information, posing substantial threats to the security and privacy of real-world ISC applications.
Simulation plays a crucial role in the verification of hardware designs, ensuring that they behave correctly before fabrication. However, traditional simulation methods can be inefficient when dealing with complex designs, especially in corner cases. To mitigate this inefficiency, Concolic testing has emerged as a promising technique, utilizing symbolic execution to guide the simulation process. However, the heuristics used in path exploration for Concolic testing often struggle with local optima, resulting in suboptimal verification outcomes and incomplete coverage of the design space. In this paper, we propose an agent-based framework to dynamically adjust path exploration strategies by leveraging beam search and large language models (LLMs). Experimental results demonstrate that this approach significantly improves branch coverage, especially for hard-to-detect branches, while also optimizing the use of computational resources.
Thermal issues are critical in 2.5D/3D IC design, and liquid cooling provides an effective solution for heat dissipation. Widely used compact thermal models (CTMs) convert chips into circuit networks for fast thermal simulations. However, current matrix-solving acceleration methods for CTM-derived circuits are inadequate for high-speed iterative transient thermal analysis of large-scale liquid-cooled 2.5D/3D ICs during design optimization. In contrast, the random walk method can provide fast solutions for local nodes in large-scale circuit networks, but it is not applicable to the circuit networks of the CTMs with liquid cooling. In this paper, we propose LCTMwalk, a novel GPU-accelerated random walk method for transient thermal analysis of liquid-cooled 2.5D/3D ICs. To enable random walks on the liquid-cooled CTM-derived circuit network, we replace the voltage-controlled current source model with the diode model. Additionally, we improve the transient analysis by using a time-backward random walk with time-domain path reuse, accelerating the solution of temperature at local circuit nodes. Experimental results show LCTMwalk can solve million-scale cases in only 500 ms, and achieves a 14-22× speedup compared to the state-of-the-art alternating direction implicit (ADI) method with GPU. Besides, LCTMwalk exhibits good generalizability and can be applied to various 2.5D/3D IC structures with high accuracy (error<1 K compared to 3D-ICE).
Analog in-memory computing (IMC) promises unprecedented energy efficiency for deep learning acceleration, but suffers from non-idealities that severely degrade inference accuracy in fabricated chips. Therefore, accurate modeling of these non-idealities becomes significant. In this work, we present PDGM-IMC, the first physics and data co-driven generative framework for IMC non-idealities characterizing. Unlike traditional physical models that fail to model complex non-ideality behaviors, or black-box neural networks that lack interpretability and generalization, PDGM-IMC leverages normalizing flows with custom transformations directly derived from device physics principles. This novel approach enables explicit modeling of complex probability distributions, spatial correlations, and die-to-die variations that previous methods could not capture. Validated on multiple dies of a commercial eFlash-based IMC SoC, PDGM-IMC improves modeling accuracy by 4.6× for the input circuit and IMC array and by 2.0× for the output circuit, significantly outperforming existing approaches. By extracting the statistical signature of fabricated chips, PDGM-IMC enables accurate pre-silicon prediction of post-silicon behavior, fundamentally transforming hardware-aware neural network optimization for analog accelerators. The source code and the pre-trained models are publicly available at https://github.com/BUAA-BASIC-Lab/PDGM-IMC.
Buffer insertion is a critical netlist optimization technique in Physical Design (PD) that balances trade-offs between Power, Performance, and Area (PPA) metrics. Traditional buffering methods rely heavily on local heuristics, which do not scale and often result in globally sub-optimal solutions. Prior Machine Learning (ML) techniques such as BufFormer attempted to alleviate this limitation but remain prohibitively time-consuming (and sub-optimal) due to their incremental nature. In this paper, we introduce BUFFALO, a generative buffer insertion framework that, for the first time in PD, formulates buffer tree generation as a sequence-to-sequence task solved by Large Language Models (LLMs). Particularly, given a design, BUFFALO performs single-shot generation of buffer trees for all fanout-violating nets and INSTA-selected timing critical nets. Furthermore, Group Relative Policy Optimization (GRPO), a Reinforcement Learning (RL) technique, is employed to refine predicted solutions in a PPA-configurable manner. Experimental results on 9 full-chip designs in a 7nm node demonstrate that BUFFALO outperforms an industry-leading commercial PD tool by 71% in Total Negative Slack (TNS), 67.69% in Worst Negative Slack (WNS), and 83x in runtime without incurring additional power consumption.
Large Language Model (LLM) inference on edge devices is crucial for democratizing AI and addressing privacy and security concerns associated with cloud services. However, the large parameter sizes of LLMs pose significant challenges in deployment on resource-constrained devices, affecting user experience. Mobile DRAM typically cannot accommodate these parameters, necessitating the use of NAND flash memory, but it has considerably slower access speeds. To overcome the limitations, we propose LLM-on-the-Palm, an LLM inference system for smartphones that leverages Processing-in-Memory (PIM)-enhanced NAND flash memory to enable fast inference of billion-parameter LLMs with minimal hardware modifications. Our approach requires only a single multiply-accumulate (MAC) unit per plane in a NAND flash memory - 256 MAC units for 256 GB SSD - without compromising cell density. Simulation results show that our design achieves ∼100 ms per token generation on a 6.7B model under specifications similar to an iPhone-15.
As silicon photonic integrated circuits (PICs) scale in density and integration level, thermal crosstalk significantly impacts chip performance and reliability, necessitating careful thermal-aware design. Traditional numerical solvers are prohibitively slow for large-scale 3D simulation, while existing machine learning surrogates struggle with generalization, especially under the complex distributed heaters and layered structures unique to PICs. We present ThermoPhoton, an operator-learning neural architecture tailored for efficient, accurate 3D thermal modeling of PICs. ThermoPhoton introduces a Pseudo-3D source representation (Pseudo-3D) that leverages device stratification, and applies Zero Coordinate Shift (ZCS) encoding to optimize physics-informed loss computation. Attention mechanisms further enhance the capture of sharp thermal gradients and crosstalk. On industry-standard benchmarks, ThermoPhoton achieves a mean absolute percentage error of 0.07%, reduces peak GPU memory by 67.1%, and shortens training time by 37.9% compared to prior operator-based methods, enabling fast, reliable, and scalable thermal analysis for next-generation photonic chips.
Hyperdimensional computing (HDC) is an emerging brain-inspired machine learning paradigm that exploits unique properties of high-dimensional vectors. HDC establishes a standard set of operations implemented by all of its classes, with Fourier and binary being the most common classes. The first achieves high accuracy but is built upon complex numbers, hindering its adoption in accelerators, whereas the latter is widely adopted in hardware despite providing lower accuracy. To overcome previous problems, the new CGR class was proposed to fit between Fourier and binary classes, learning better than the binary class at affordable hardware implementation w.r.t. Fourier. This paper introduces Hyle, an HLS-based framework for building HDC accelerators in CGR and binary for FPGAs. Hyle is the first proposal to accelerate CGR. We show that the learning advantage of CGR over BSC can result in faster and smaller accelerators and reduce model size up to 8× at iso-accuracy compared to binary.
Reliable, generalizable data foundations are critical for enabling large-scale models in computational lithography. However, essential tasks—mask generation, rule violation detection, and layout optimization—are often handled in isolation, hindered by scarce datasets and limited modeling approaches. To address these challenges, we introduce Unitho, a unified multi-task large vision model built upon the Transformer architecture. Trained on a large-scale industrial lithography simulation dataset with hundreds of thousands of cases, Unitho supports end-to-end mask generation, lithography simulation, and rule violation detection. By enabling agile and high-fidelity lithography simulation, Unitho further facilitates the construction of robust data foundations for intelligent EDA. Experimental results validate its effectiveness and generalizability, with performance substantially surpassing academic baselines.
