Motivated by the stringent requirements of the Upstream Pixel (UP) tracker in the LHCb Upgrade II and the Inner Tracking detector (ITK) of the Circular Electron Positron Collider, the COFFEE series of pixel sensor chips have been developed using a 55 nm High-Voltage CMOS (HVCMOS) process. The primary objective is to achieve a time resolution of a few nanoseconds under a hit density of up to 100 MHz/cm(2), while maintaining fine spatial resolution (similar to 10 mu m) and reasonable power consumption (<200 mW/cm(2)). Building on the process validation of the COFFEE2 prototype, this work presents the design and preliminary test results of COFFEE3 - a prototype integrating two distinct readout architectures. Architecture 1, tailored for the current triple-well process, adopts NMOS-only in-pixel circuitry and innovative column-level readout to handle high hit densities. The time walk of pixel-level signal is controlled within 10 ns, and the Time of Arrival (TOA) and Time over Threshold (TOT) are measured with a system clock with the period of 25 ns in peripheral circuits. Architecture 2, developed for future possible processes with p-type buried layer isolation, features pixel-level time measurement and storage. A chip-level Time-to-Digital Converter (TDC) is used and the part of Voltage-Controlled Delay Line (VCDL) is copied in each pixel to get a high time resolution. The TOA resolution is estimated to be 4.2 ns and the TOT resolution 8.4 ns. COFFEE3, with a layout size of 3 & times;4 mm(2), was manufactured and has undergone preliminary tests. Charge injection tests for analog circuits, and laser tests for full readout chains, confirm that both architectures operate as expected. Next step work will focus on characterizing key performance such as the timing resolution, radiation hardness, and tracking performance of minimum ionising particles.

Triple Modular Redundancy (TMR) technology has been implemented in the design of the HCCStar to reduce digital state changes and ensure reliable operation. We tested the effectiveness of the protection by placing HCCStar chips in a proton beam. We studied corrected bit flips in registers and actual single event effects in the LCB and LP paths under different proton energies. Our estimate is that the LP data-loss fraction relative to the 400 kHz readout is O(10^-10) during normal operation and there will be O(10) corrected bit flips per HCCStar bit per year at the HL-LHC.

The Circular Electron Positron Collider (CEPC) is a next-generation electron-positron collider for precision studies of Higgs, flavor physics and beyond. A key component of its tracking system is the Inner Tracker (ITK) using High Voltage Complementary Metal-Oxide-Semiconductor (HV-CMOS) sensor technology. The CEPC ITK consists of three barrel layers and four pairs of endcap disks, covering a total active area of about 20 m2. The HV-CMOS sensor fabricated with advanced 55 nm process is used to achieve a few-micrometer spatial resolution and a few-nanosecond timing resolution, with a moderate power consumption. The module design is shared between barrel and endcap to facilitate production. The whole system is designed for minimal material budget, with 0.7% X0 per layer in the barrel part. The design has been implemented in CEPC software framework for performance study and future optimization.

The Circular Electron-Positron Collider (CEPC), as the next-generation electron-positron collider, is tasked with advancing not only Higgs physics but also the discovery of new physics. Achieving these goals requires high-precision measurements of particles. Taichu seires, Monolithic Active Pixel Sensor (MAPS), a key component of the vertex detector for CEPC was designed to meet the CEPC's requirements. For the geometry of vertex detector is long barrel with no endcap, and current silicon lacks a complete digitization model, precise estimation of cluster size particularly causing by particle with large incident angle is needed. Testbeam results were conducted at the Beijing Synchrotron Radiation Facility (BSRF) to evaluate cluster size dependence on different incident angles and threshold settings. Experimental results confirmed that cluster size increases with incident angle. Simulations using the Allpix^2 framework replicated experimental trends at small angles but exhibited discrepancies at large angles, suggesting limitations in linear electric field assumptions and sensor thickness approximations. The results from both testbeam and simulations have provided insights into the performance of the TaichuPix chip at large incident angles, offering a crucial foundation for the establishment of a digital model and addressing the estimation of cluster size in the forward region of the long barrel. Furthermore, it offers valuable references for future iterations of TaichuPix, the development of digital models, and the simulation and estimation of the vertex detector's performance.

A high precision beam monitor system based on silicon carbide PIN sensor is designed for China Spallation Neutron Source 1.6 GeV proton beam to monitor the proton beam fluence.The concept design of the beam monitor system is finished together with front-end electronics with silicon carbide PIN sensors, readout system and mechanical system.Several tests are performed to study the performance of each component of the system.The charge collection of the SiC PIN sensors after proton radiation is studied with 80 MeV proton beam for continuous running. Research on the performance of the front-end electronics and readout system is finished for better data acquisition.The uncertainty of proton beam fluence is below 1

The proposed Circular Electron Positron Collider (CEPC) presents several challenges for the vertex detector, including material budget, spatial resolution, readout speed, and power consumption. To address these challenges, a Monolithic Active Pixel Sensor (MAPS) prototype called TaichuPix has been developed for the CEPC vertex detector. To evaluate the performance of the TaichuPix-3 prototype, a beam test was conducted at the DESY II TB21 facility. This work presents the analysis results of the offline beam data, including cluster size, spatial resolution, and multiple scattering studies, which indicate the intrinsic resolution of TaichuPix-3 chips is less than 5 mu m and the material budget is measured to be 0.170 +/- 0.018%.

High-Voltage CMOS (HVCMOS) sensors, featuring a deep n-well separating the transistors and the depletion region, are intrinsically radiation hard and a good candidate for tracking systems in future high energy physics experiments. In hope of reducing the power density and incorporating more functionality in the same area, we are looking for foundries where HVCMOS sensors can be implemented in smaller feature size. In this paper we report the feasibility study in two MPWs using 55 nm processes. Sensor diodes are designed with deep n-well serving as electrode in Low-Leakage process, and the test results are reported. Design and first results for MPW in 55 nm HVCMOS process will also be described.

A high-precision beam monitor system based on silicon carbide PIN sensor is designed for the 1.6 GeV proton beam of China Spallation Neutron Source. The conceptual design of the beam monitor system is composed of front-end electronics with SiC PIN sensor and readout system. The charge collection efficiency of the SiC PIN sensor after proton radiation is studied with 80 MeV proton beam. 98 % in the beam monitor system. The results reveal that the beam monitor system can be used for the 1.6 GeV proton beam of China Spallation Neutron Source.

The Circular Electron Positron Collider (CEPC) has been proposed to enable more thorough and precise measurements of the properties of Higgs, W, and Z bosons, as well as to search for new physics. In response to the stringent performance requirements of the vertex detector for the CEPC, a baseline vertex detector prototype was tested and characterized for the first time using a 6GeV electron beam at DESY II Test Beam Line 21. The baseline vertex detector prototype is designed with a cylindrical barrel structure that contains six double-sided detector modules (ladders). Each side of the ladder includes TaichuPix-3 sensors based on Monolithic Active Pixel Sensor (MAPS) technology, a flexible printed circuit, and a carbon fiber support structure. Additionally, the readout electronics and the Data Acquisition system were also examined during this beam test. The performance of the prototype was evaluated using an electron beam that passed through six ladders in a perpendicular direction. The offline data analysis indicates a spatial resolution of about 5 μm, with detection efficiency exceeding 99% and an impact parameter resolution of about 5.1 μm. These promising results from this baseline vertex detector prototype mark a significant step toward realizing the optimal vertex detector for the CEPC.

This is the first study of the ABCStar V1 chips with an 80 MeV proton beam from CSNS. The ITk strip upgrade project utilizes the custom ABCStar ASIC, employing Triple Modular Redundancy technology to enhance its resistance to Single Event Effects caused by radiation. We tested the effectiveness of the radiation protections by operating the ASICs within a proton beam. This paper introduces the analysis of logic upsets for the production version of the ABCStar ASIC with a single -chip test system at the proton beam platform of the CSNS. The study of logic upsets in pipeline and registers was carried out at 80 MeV. Bit flips in the ABCStar V1 with Triple Modular Redundancy protections are reduced significantly as expected. We have also observed that proton beam at this energy level may have an impact on the chip itself, potentially changing the operating mode of chips, which was not observed previously.

The proposed Circular Electron Positron Collider (CEPC) imposes new challenges for the vertex detector in terms of pixel size and material budget. A Monolithic Active Pixel Sensor (MAPS) prototype called TaichuPix, based on a column drain readout architecture, has been developed to address the need for high spatial resolution. In order to evaluate the performance of the TaichuPix-3 chips, a beam test was carried out at DESY II TB21 in December 2022. Meanwhile, the Data Acquisition (DAQ) for a multi-plane configuration was tested during the beam test. This work presents the characterization of the TaichuPix-3 chips with two different processes, including cluster size, spatial resolution, and detection efficiency. The analysis results indicate the spatial resolution better than 5 µm and the detection efficiency exceeding 99.5 % for TaichuPix-3 chips with the two different processes.

The proposed Circular Electron Positron Collider (CEPC) imposes unique requirements on the vertex detector. In response, the MOST1 and MOST2 projects were launched with the aim of developing a fully functional pixel sensor and implementing the prototype of the inner tracking detector. To efficiently manage the data flow from multiple sensors, specialized readout electronics are required. In order to evaluate the MOST2 project indicators set for the vertex detector prototype, a beam telescope was constructed using six TaichuPix-3 sensor chips and applied in different experiments. The experimental results demonstrate that the telescope functions effectively and that the detector prototype meets the design objectives of the MOST2 project. This project encompasses the design of the readout electronics, the functionality of the readout system, the architecture of the telescope, and the specifics of the telescope experiments.

The proposed Circular Electron Positron Collider poses significant challenges for the vertex detector in terms of material budget, spatial resolution, readout speed, and power consumption. To address these challenges, a Monolithic Active Pixel Sensor prototype, named TaichuPix, has been developed based on a column drain readout architecture. The performance of the second version of this prototype, TaichuPix2, has been evaluated using a radioactive source, which exhibits a time walk of less than 100 ns corresponding to the threshold of 380 e− and amplitude variation of analog output from 300 mV to 500 mV. An infrared laser setup is utilized to estimate the single-point spatial resolution of this sensor for minimum-ionizing particles. The setup includes a high-precision three-dimensional translation stage and an optical system with a 1064 nm laser diode. With this setup, the spatial resolution is estimated to be about 4 µm. The performance for real particles is to be confirmed in a test beam.

The proposed Circular Electron Positron Collider (CEPC) imposes new challenges for the vertex detector in terms of material budget, spatial resolution, readout speed, and power consumption. It is necessary to design and construct the CEPC vertex detector with state-of-the-art silicon detector technologies. A dedicated CMOS Pixel Sensor chip, named TaichuPix, is being developed for the first 6-layer CEPC vertex detector prototype. The TaichuPix development is based on a fast in-pixel readout combined with a hit-driven architecture, which would be beneficial for the high hit rate. This work reports the requirements for the sensor and the design approach being followed to cope with it. Two small-scale prototypes (25 mm2) capable of achieving a hit rate up to 36 MHz/cm2, were designed in a 180 nm CMOS process. One of them, the TaichuPix-2 prototype was characterized with electrical and radioactive sources in the laboratory. The test results on the chip functionality and the pixel performance in terms of threshold and noise as well as the timing response are reported.

The proposed Circular Electron Positron Collider (CEPC) imposes new challenges for the vertex detector in terms of high resolution, low material, fast readout and low power. The Monolithic Active Pixel Sensor (MAPS) technology has been chosen as one of the most promising candidates to satisfy these requirements. A MAPS prototype, called TaichuPix1, based on a data-driven structure, together with a column drain readout architecture, benefiting from the ALPIDE and FE-I3 approaches, has been implemented to achieve fast readout. This paper presents the overall architecture of TaichuPix1, the experimental characterization of the FE-I3-like matrix, the threshold dispersion, the noise distribution of the pixels and verifies the charge collection mechanism using a radioactive source. These results prove that the digital periphery and serializer are able to transmit the collected charge to the data interface correctly. Moreover, the individual self-tests of the serializer verify that it can work up to about 3 Gbps, while they also indicate that the analog front-end features a fast-rising signal with a short time walk and that the FE-I3-like in-pixel digital logic is properly operating at the 40 MHz system clock.

For the Phase-II Upgrade of the ATLAS Detector [1], its Inner Detector, consisting of silicon pixel, silicon strip and transition radiation sub-detectors, will be replaced with an all new 100% silicon tracker, composed of a pixel tracker at inner radii and a strip tracker at outer radii. The future ATLAS strip tracker will include 11,000 silicon sensor modules in the central region (barrel) and 7,000 modules in the forward region (end-caps), which are foreseen to be constructed over a period of 3.5 years. The construction of each module consists of a series of assembly and quality control steps, which were engineered to be identical for all production sites. In order to develop the tooling and procedures for assembly and testing of these modules, two series of major prototyping programs were conducted: an early program using readout chips designed using a 250 nm fabrication process (ABCN-250) [2, 3] and a subsequent program using a follow-up chip set made using 130 nm processing (ABC130 and HCC130 chips). This second generation of readout chips was used for an extensive prototyping program that produced around 100 barrel-type modules and contributed significantly to the development of the final module layout. This paper gives an overview of the components used in ABC130 barrel modules, their assembly procedure and findings resulting from their tests.

Monolithic silicon sensors developed with High-Voltage CMOS (HV-CMOS) processes have become highly attractive for charged particle tracking. Compared with the standard CMOS sensors, HV-CMOS sensors can provide larger and deeper depletion regions that lead to larger signals and faster charge collection. They can provide high position resolution, low material budget, high radiation hardness and low cost that are desirable for high performance tracking in harsh collision environment. Various studies have been conducted to explore the technology feasibility for the large-area tracking systems at future collider experiments. CHESS (CMOS HV/HR Evaluation for Strip Sensor) sensor series have been developed as an alternative solution to the conventional silicon micro-strip detectors for the ATLAS inner tracker upgrade. The first prototype (named CHESS1) was to evaluate the diode geometry and the in-pixel analog electronics. Obtained test results were used to optimize the second prototype (named CHESS2). CHESS2 was implemented with a full digital readout architecture and realized as a full reticle sized monolithic sensor. In this paper, the basic characteristics of the CHESS2 prototype sensors and their performance in response to different input signals are presented.

The proposed Circular Electron-Positron Collider (CEPC) presents new challenges for pixel detectors in terms of cell size and functionality. A high data rate digital design and readout architecture of a Monolithic Active Pixel Sensor (MAPS) prototype for the CEPC vertex detector is presented. The MAPS prototype, together with the column drain based readout architecture, benefiting from the ALPIDE (ALice PIxel DEtector) and FE-I3 approaches, has been implemented to achieve high spatial resolution, fast readout, and low power consumption. The simulation results indicate the readout logic works properly with input data rates of 120MHz; while both analog front-end and in-pixel readout logic meet the 25ns bunch spacing constraint.

CMOS Pixel Sensors (CPS) are attractive for CEPC vertex detector construction due to its high granularity, high speed, low material budgets, low power and potential high radiation tolerance. The characteristics of the sensing diode and the readout architecture were studied using several chips with small-scaled pixel array for CEPC vertex detector. This paper will study the design of a high data-rate readout logic design of a 512 x 1024 pixel array. For the innermost layer of CEPC vertex detector, the hit pixel frequency is near 120 MHz, which is several times higher than the design requirements of ALPIDE for ALICE vertex detector. Based on the hit-driven readout scheme in the pixel array of ALPIDE and FEI3, we propose a new peripheral readout logic design. All the double columns of pixels are read out in parallel and a fast readout architecrue of 512 double columns is realized. Meanwhile, a real-time data compression and a trigger-mode operation are supported to reduce the data output. The simulation results indicate the pixel hit frequency in average of 120 MHz can be processed with readout time of 50 ns per pixel and of less than 500 ns per double column of pixels. The layout area is 25.68 x 1.13 mm(2). The power density in trigger mode and in triggerless mode are estimated as 25 similar to 30 mW/cm(2) and 35 similar to 45 mW/cm(2) respectively.