Perpendicular recording—a new paradigm for high-density magnetic recording currently under intensive development—presents complex engineering challenges which require that design be assisted by computer simulation. However, simulating perpendicular recording is itself a challenge for several reasons; it requires a large simulation box that includes both write head and hard disk and must be treated at high spatial resolution, and the simulations must run for long periods of time and for numerous data inputs. To accomplish this complex modeling, we have developed novel techniques which involve a mixed real-space/Fourier-space representation and which compute time scales linearly with system size, enabling large simulations to be performed efficiently. We show tests of our methodology and provide an example of a simulation that involves writing three bits (a tribit) to disk.

Recent advances in magnetic recording technology are increasing the relevance of simulation to magnetic media design. In particular, the difficulties inherent in developing perpendicular recording technology require the write process to be modeled at an integrated level via the simulation of a nanoscale machine consisting of the media, the soft underlayer, and the moving head. These simulations need to be very efficient in order to permit extensive testing of both materials and drive specification. Thus, significant methodological improvements that increase the accuracy and speed of the micromagnetic modeling are required. In this article, a method for calculating the magnetic fields in a complex layered material with grained morphologies whose computational cost scales linearly with system size is presented. The speed, accuracy, and parallel efficiency of the method is demonstrated on both supercomputers and PC clusters using our Almaden-Yorktown micromagnetic simulator (AYM). The method and AYM software are then used to perform an example simulation of perpendicular magnetic recording, writing a “tribit” in a grained data layer.

Let a k-partition of a graph be a division of the vertices into k disjoint subsets containing m1 ≥ m2,..., ≥mk vertices. Let Ec be the number of edges whose two vertices belong to different subsets. Let λ1 ≥ λ2, ..., ≥ λk, be the k largest eigenvalues of a matrix, which is the sum of the adjacency matrix of the graph plus any diagonal matrix U such that the suomf all the elements of the sum matrix is zero. Then Ec ≥ 1/2Σr=1k-mrλr. A theorem is given that shows the effect of the maximum degree of any node being limited, and it is also shown that the right-hand side is a concave function of U.C omputational studies are madoef the ratio of upper bound to lower bound for the two-partition of a number of random graphs having up to 100 nodes.

The delays at all sink nodes were measured using the two-pole circuit sim-ulator proposed by Zhou et al. 17] and discussed in 3]. This simulator is a computationally eecient code which has produced very accurate results (within a few percent) when tested against SPICE. We consider both the average delay (taken over all sinks) and the worst-case delay (i.e., the latest arrival time of the signal to any sink); all results are normalized to the corresponding values for the MST routing. We make the following observations. 1. While BRBC tends to yield lower tree cost for any xed , if we consider the family of trees over each instance, we see that the AHHK solution will almost always have lower cost for any given tree radius. 2. AHHK yields lower worst-case and average-case signal delay than BRBC (Table 2). As nets become larger, MST radius becomes quite large, and the delay improvements from the AHHK solution become more obvious. 3. While tree cost closely reeects Elmore delay in the IC technology, diierences between the algorithms are small since both will closely approximate the MST for those values of that minimize delay. On the other hand, since tree radius is dominant for MCM interconnects, AHHK is superior in this technology since it gives less cost for a given radius. 4. For each instance of each net size, we recorded the c and values that aaorded lowest signal delay over the entire family of 21 trees generated by each algorithm. The average \best" parame-terization is reported in Table 3, and is useful in guiding the application of AHHK when it is too expensive to generate an entire family of trees. 5 Conclusions Analysis of distributed RC delay shows that performance-driven routing requires tree constructions that can trade oo cost and radius according to interconnect technology and net size. Previous approaches 2, 4, 10] essentially rely on a depth rst traversal of the MST and insert shortest paths as needed to maintain a prescribed radius bound. In contrast, our new AHHK approach directly combines the recurrences for Prim's MST algorithm and Dijk-stra's SPT algorithm. The result is an elegant trade-oo between radius and cost which empirically yields lower-cost trees than the BRBC algorithm 4] for any given tree radius. Simulation results show that the AHHK algorithm constructs routing trees with sig-niicantly less maximum and average delay than the BRBC method 4], in both …

It is shown from simple theoretical considerations that the distribution ƒk of wire lengths for a good two-dimensional placement on a square Manhattan grid should be of the form ƒk = g/kγ (1 ≤ k ≤ L) and ƒk ≈ 0 (k > L), where γ is related to the Rent partitioning exponent p by the equation 2p + γ ≈ 3. Three placements were investigated and the distribution functions for wire length were found to follow the above relationships.

This paper describes a channel routing wiring program and its interface to the user. Of particular interest are its interface facilities, which permit manual update of the routing, pre-routing, and incremental routing. A hierarchical organization of the logic is feasible, which permits moving of complex entities, such as latches, adders and others, as complete entities. The internal wiring of these entities could either be done manually and be fixed before layout, which would be desirable when the wiring was used as a delay line, or could be left to the wiring program, which would route them more flexibly. The features above are made possible by the special-interface organization used here. In this interface the pins on the devices can be directly addressed, relatively addressed, and indirectly addressed; a simple macrocompiler permits the hierarchical organization of the data.

The length of the interconnections for a placement of logic gates is an important variable in the estimation of wiring space requirements, delay values, and power dissipation. A formula for an upper bound on expected average interconnection length, based on partitioning results, is given for linear and square arrays of gates. This upper bound gives significantly lower interconnection length than the bound based upon random placement. Actual placements give average interconnection lengths of about half the upper bound given by theory.

An algorithm for generating test patterns for combinational circuits has been developed and programmed. The algorithm is definitive and finds a test for all faults including those that require multiple paths to be sensitized, by sensitizing a single path at a time and trying at most each single path. This is achieved by using a new calculus based on nine values (0,1,D,D̄,0/D,0/D̄, 1/D,1/D̄,U). One path is deliberately sensitized while the alternative paths are assigned values which permit the option of desensitizing or sensitizing them as the sensitized path is developed. Experimental results are presented for a variety of cases.

Properties of the sum of the q algebraically largest eigenvalues of any real symmetric matrix as a function of the diagonal entries of the matrix are derived. Such a sum is convex but not necessarily everywhere differentiable. A convergent procedure is presented for determining a minimizing point of any such sum subject to the condition that the trace of the matrix is held constant. An implementation of this procedure is described and numerical results are included. Minimization problems of this kind arose in graph partitioning studies [8]. Use of existing procedures for minimizing required either a strategy for selecting, at each stage, a direction of search from the subdifferential and an appropriate step along the direction chosen [10,13] or computationally feasible characterizations of certain enlargements of subdifferentials [1,6] neither of which could be easily determined for the given problem. The arguments use results from eigenelement analysis and from optimization theory.

A model of the design process for computer logic is used to estimate the number of bits of memory required to replace a so-called “random logic” circuit. The model can also be used to compare the respective time delays of array logic and random logic.

A new suboptimal intermediate-speed algorithm which use n2 In n steps is developed for the assignment problem. Upper and lower bounds are derived, using this algorithm and other methods, for the average values of three classes of n × n assignment problems: 1. When the elements of the matrix are random numbers uniformly distributed over the range 0 to 1, the average optimal value is smaller than 2.37 and larger than 1 for problems with large n. Experimentally the value is about 1.6. 2. When the elements of the matrix are random numbers such that the probability of being less than x is xk+1 (k ≠ 0), asymptotic expressions for the upper and lower bounds of the average optimal value are Cknk/(k+1) and Ck[(k+1)/k]nk/(k+1) respectively. 3. When each column of the matrix is a random permutation of the integers 1 to n, asymptotic upper and lower bounds are 2.37n and 1.54n, respectively. Experimentally the value is about 1.8n.

The statistics of placing vertices of a graph on a square array of points is developed for several classes of graphs. Distribution functions for the lengths to be associated with edges are given. A lower bound is devised for the average value within each class of the lowest placement distance of a graph. For one class of graphs, this is compared with values devised from actual placements of a random set of representatives, and it can be seen that the lower bound devised here comes close to the actual value for the average minimum distance. A highly approximate formula is derived for one class of graphs (the simplest of the three classes considered) and is given by (19): \[ {\tilde{\mathcal{L}}}_{\min } = N\frac{{C^{1/2 - C /2N}}}{{e^{1 - C/2N}}} \] where C is the number of vertices in the graph and N is the number of edges, while ${\tilde{\mathcal{L}}}_{\min} $ is our lower bound on the average of the minimum distance of the placements of the graphs. The relationship to the quadratic assignment problem is shown, as well as how the theory can be extended to cover the case of net routing.

Design and fabrication techniques for wiring pattern used for interconnecting network circuits of automatic mask sets