Phase-locked loops (PLLs) with a sawtooth phase detector (PD) characteristic arise in digital implementations employing flip-flop-based phase detectors and are widely used in synchronization and carrier-recovery applications. The corresponding baseband model is discontinuous, requiring a solution concept beyond classical ODE theory. This paper analyzes a second-order PLL with a lead-lag loop filter and a sawtooth PD characteristic using the Filippov approach for differential inclusions. Exact pull-in range formulas are derived for both lag and lead-lag filters, and the corresponding bifurcation diagrams are constructed. The analysis fills a gap left by early works, which relied on a conjecture about discontinuity crossings. Theoretical results are validated by simulation of both the flip-flop digital PLL and the corresponding baseband model with a sawtooth characteristic.
This paper presents a 9-bit 16-GS/s 8-way time-interleaved pipelined-SAR ADC in 28-nm CMOS. A DC-coupled current-mode global dither injection eliminates the signal perturbation caused by capacitor-coupled injection, enabling background gain and offset calibration that is inherently global and buffer-topology-independent. A complementary dynamic amplifier (CDA) with a dynamically biased inverter-based expansive transconductance cell improves linearity by up to 20dB across PVT, while the output reset and tail degeneration in CDAs suppress common-mode (CM) gain for stable pipeline operation. Running at 16GS/s, the ADC dissipates 150mW and occupies 0.179mm(2), achieving 47.17-dB SNDR, a 154.3-dB Schreier FoM, and a 50.6-fJ/conversion-step Walden FoM, with calibration. The performance stays robust over +/- 5% supply and -20to 90 degrees C across three chips.
Attention-based artificial intelligence (AI) models have achieved remarkable success in natural language processing (NLP) and computer vision (CV), yet their edge deployment is limited by computing and memory resources. Although memristor crossbar arrays provide high-density storage and efficient in-memory computing capability, the nonlinearity of softmax in attention mechanisms still imposes substantial hardware cost. To mitigate this issue, we propose a stagewise quantization scheme with tunable precision to achieve a favorable tradeoff between model accuracy and hardware complexity. A memristor-based parallel two-dimensional lookup table (2D-LUT) engine with a CAM-based decoder is designed to enable division-free lookup computation. Furthermore, an efficient parallel softmax computation architecture based on memristor arrays is presented. Based on measurement-informed analog simulations and gate-level digital simulations in a 40-nm CMOS technology, the proposed softmax computation scheme achieves a per-stage peak throughput of 1.2 G/s. Using real softmax-input traces sampled from BERT-base on the QNLI dataset, MobileViT-xxs on the ImageNet-1k dataset, and Qwen3.5-0.8B on the BoolQ dataset, the proposed scheme delivers energy efficiencies of 2.85 TOPS/W, 2.00 TOPS/W, and 2.47 TOPS/W, respectively. These results are 2.9 & times; to 6.1 & times; higher compared with the energy efficiency of the state-of-the-art memristor-based softmax designs while incurring less than 0.3% accuracy loss across representative AI tasks and models.
This article presents a 20-Gb/s transition-detection-based transceiver (TD-TRX) for on-chip global data bus and high-bandwidth memory interfaces. In such links, conventional voltage-detection-based transceivers (VD-TRXs) are susceptible to pre- and post-cursor inter-symbol interference (ISI) and low-frequency supply noise. In contrast, the proposed TD scheme detects data using transition information. It inherently attenuates the impact of higher-order ISI terms, provides robustness against low-frequency supply noise without complex circuitry, and ensures reliable operation under various RC-dominant channel-length conditions. On the TX side, energy efficiency is improved by segmenting and co-optimizing the main driver and pre-drivers to adapt the effective driver bandwidth according to channel loss, resulting in a 37.9% reduction in TX power consumption under short-channel conditions. Fabricated in a 28-nm CMOS process, the prototype chip achieves competitive figures of merit of 62.5 fJ/b/mm and 23.6 fJ/bit/dB, demonstrating robust operation and improved energy efficiency over various channel lengths.
Strong adjacent blockers can degrade OFDM receivers through reciprocal-mixing phase-noise (PN) distortion, which spreads blocker energy into the desired band before channel-selective filtering. Prior dual-path PN-cancellation receivers suppress this distortion by exploiting a deterministic PN relationship between two downconversion paths, but their symmetric LO-frequency plan restricts carrier-frequency agility and their frequency-flat combining is poorly suited to wideband inter-path mismatch. This paper presents a frequency-agile LO-path-realigned dual-path receiver architecture with frequency-domain reciprocal-mixing PN cancellation. The proposed architecture forms the effective downconversion LOs in the LO-generation path using two oscillator domains, allowing a fixed IF filtering structure while preserving the source-tone PN relationship needed for cancellation. To support wideband OFDM, a subband combiner is developed to track frequency-selective inter-path mismatch. A discrete-component prototype using a ring-oscillator-like PN profile validates the approach with a 5MHz packet-based OFDM waveform and an adjacent OFDM blocker. Measurements show that the subband combiner consistently provides the highest decoded SNR at large blocker powers and preserves effective reciprocal-mixing PN suppression under an LO-path-realigned frequency plan.
