This paper presents a procedure for extracting the threshold voltage and mobility degradation of a MOS tran sistor within a class-A power amplifier (PA) that suffers from aging. The procedure does not require electrical measurements and is non-invasive, as it is based solely on performing temperature measurements while the PA is operating in different situations. Experimental validation is performed on four IC samples that contain a PA and a differential temperature sensor. Accelerated aging is applied to the four samples, and the values extracted from the temperature sensor are compared with the values obtained using electrical measurements. The error is in all cases below 10%, thus demonstrating the possibility of on-line monitoring of MOS parameters with good accuracy.

One of the threats to nanometric CMOS analog circuit reliability is circuit performance degradation due to transistor aging. To extend circuit operating life, the bias of the main devices within the circuit must be adjusted while the aging degradation process affects them by using a monitor circuit that tracks the evolution of the circuit performance. In this paper, we propose the use of DC temperature measurements in the proximity of the circuit to perform the monitoring of circuit performance degradation and as an observable variable to adjust the bias of the main devices to restore the degraded performance to the original values. To this end, we present experimental results obtained from nine samples of a standard CMOS integrated circuit containing a high-frequency class-A power amplifier and a differential temperature sensor. After accelerated aging, the gain of the amplifier is degraded up to 50%. We propose two different procedures to perform DC temperature measurements that allow tracking of the amplifier gain degradation due to aging and, by uniquely observing temperature readings, automatically set a new bias for the amplifier devices that restores the original amplifier gain. Whereas one of the procedures is able to restore the gain up to a certain limit, the second allows full gain restoration.

This paper describes the Sargantana System on chip (SoC), a 64-bit RISC-V single core processor designed by a number of academic institutions and manufactured in 22 nm FDSOI technology: BSC, UPC, UB, UAB, CIC-IPN and IMB-CNM (CSIC). The SoC includes the processor as well as, among other components, a Phase Locked Loop (PLL) operating up to 2 GHz, interfaces to HyperRAM and a Serdes up to 8 Gbps. The processor has demonstrated experimental correct operation at 800 MHz.

In this work, CMOS inverters are subjected to electrical stress emulating a complete operation cycle and the shifts in the performance parameters (i.e., peak current and inversion voltage) evaluated. Moreover, degradation of the two MOSFETs is also measured as variations of their threshold voltage and mobility. The relationships between the observed transistors and circuit parameter shifts are explained in terms of the different device aging mechanisms (i.e., BTI, CHI and OFF-state) that are active depending on the voltages at the circuit terminals. Moreover, the combined effects of the aging mechanisms that are sequentially activated, at device and circuit levels, and their voltage dependence, are also discussed. Finally, a power law fitting of the inversion voltage degradation of the inverter is used to evaluate its variation at operating conditions.

This paper presents the design of an RF receiver front-end for IoT application, integrating a low noise amplifier (LNA) and an active mixer. The circuit is designed in 28-nm FDSOI technology, to operate on the ISM 2.4-2.5 GHz band. The inductor-less LNA exploits the parasitic package inductance as resonant load, limiting chip area and costs. The receiver, designed for the stringent requirements of the application, operates with a voltage supply of 0.35 V, and it exhibits in simulation a power consumption below 45 μW. Besides, it achieves a voltage gain of 27.4 dB, a Third Order Input Intercept Point (IIP3) of -26.8dBm, and a noise Figure (NF) of 12.8 dB, with an intermediate frequency (FI) of 2 MHz. The small area of only 0.0021 mm2, combined with the low power consumption and operating voltage, makes the proposed RF receiver well-suited for the IoT application domain.

The characterization of the MOSFET Time-Dependent Variability (TDV) can be a showstopper for reliability-aware circuit design in advanced CMOS nodes. In this work, a complete MOSFET characterization flow is presented, in the context of a physics-based TDV compact model, that addresses the main TDV characterization challenges for accurate circuit reliability prediction at design time. The pillars of this approach are described and illustrated through examples.

An extensive experimental analysis of the hot carrier injection (HCI) and bias temperature instability (BTI) aging effects on RF linear power amplifiers (PAs) is presented in this article. Two different 2.45-GHz PA topologies have been implemented in a CMOS 65-nm technology: one based on a classical common-source (CS) and choke inductor and another one based on a complementary current-reuse (CR) circuit, both of them producing similar gain and output 1-dB compression point (P -1dB ). These circuits have been stressed to produce accelerated aging degradation, by applying increasing supply (V DD ) voltages or increasing RF input powers (PIN). The degradation on the transistor parameters (threshold voltage and mobility), dc bias point (I dc current), and RF performance (gain, matching, and compression point) has been simultaneously measured. This has allowed us to observe how the reduced transistor degradation in CR PA results in higher robustness in its RF parameters compared with the CS PA circuit. The equivalent root-mean-square (rms) voltages have been proposed as an observable metric to assess the combined dc + RF stress in a PA circuit. This has been applied to a semianalytical model, providing comprehension of the link between the conditions under which a circuit is operated, the degradation of the transistor parameters, and the effects on the dc current and RF performance.

In this work, the degradation of the transistors in a CMOS inverter under the various biasing configurations in a complete operation cycle and their impact on the circuit performance are experimentally studied. The relationships between transistors parameters (threshold voltage and mobility) and circuit specifications shifts (peak current and inversion voltage) are explained in terms of the different device aging mechanisms that are active depending on the voltages at the circuit terminals. Moreover, the combined effects of the different aging mechanisms sequentially activated (such as BTI, HCI and OFF-state), at device and circuit levels, emphasizing the role of the OFF-state degradation, are also discussed.

A new sensor topology meant to extract figures of merit of radio-frequency analog integrated circuits (RF-ICs) was experimentally validated. Implemented in a standard 0.35 μm complementary metal-oxide-semiconductor (CMOS) technology, it comprised two blocks: a single metal-oxide-semiconductor (MOS) transistor acting as temperature transducer, which was placed near the circuit to monitor, and an active band-pass filter amplifier. For validation purposes, the temperature sensor was integrated with a tuned radio-frequency power amplifier (420 MHz) and MOS transistors acting as controllable dissipating devices. First, using the MOS dissipating devices, the performance and limitations of the different blocks that constitute the temperature sensor were characterized. Second, by using the heterodyne technique (applying two nearby tones) to the power amplifier (PA) and connecting the sensor output voltage to a low-cost AC voltmeter, the PA's output power and its central frequency were monitored. As a result, this topology resulted in a low-cost approach, with high linearity and sensitivity, for RF-IC testing and variability monitoring.

In this work, an `on-the-fly' type technique for the characterization and monitoring of the CMOS inverter degradation, simultaneously to the application of pulsed voltage stresses, is presented. This technique allows analyzing the CMOS inverter performance degradation through the inversion voltage shifts measured during the application of rapid pulses. The observed degradation of the inversion voltage is described by an analytical equation that considers only the shifts of two device parameters, threshold voltage and mobility, of both transistors of the CMOS inverter.

The high-frequency operation of RF circuits poses additional challenges to the prediction of their reliability during the initial design phase. Among them, the availability of device compact models that describe their aging under RF conditions and the model experimental validation at circuit level. In this work, RF test circuits that allow establishing device-circuit aging correlations are described. Two different 2.45 GHz power amplifier circuits with similar performance, implemented in a 65 nm CMOS technology, have been designed and experimentally characterized. Results demonstrate the importance of the topology selection to guarantee robustness against aging effects, and thus the need to predict their parameter degradation during the initial design phase, accounting for the actual DC and RF device operation conditions. With that purpose, we propose a semi-empirical MOSFET compact model that, based on the RMS equivalent voltages at the transistor terminals when operated within a RF circuit, can provide an accurate estimation of the device and circuit degradations.

This paper analyzes the potential benefits of FDSOI technology for the design of Ultra-Low Voltage, Ultra-Low Power Low-Noise Amplifiers (LNA) targeting the Internet-of-Things paradigm. For that purpose, three preliminary designs of 2.4 GHz LNAs based on different circuit solutions are presented. Designs based on inductive source generation and transformer feedback gm-boosting topologies show potential operation at V DD =250 mV, producing S 21 above 15 dB and NF in the range 5-7 dB with a power consumption of only 50 μW. Implementation of those circuits solutions in an advanced 28nm FDSOI technology is inconvenient though, due to the required on-chip inductors that take a large and expensive silicon area. On the contrary, a third design based on current-reuse active gm-boosting would occupy small silicon area and would benefit from the characteristics of FDSOI technology. Pre-layout simulation results show the possibility to reduce supply voltage to only V DD =350 mV when FBB is applied, producing S 21 of 24 dB and NF of 2.2dB with a power consumption of only 12.5 μW. This performance compares favorably against similar ULP-ULV LNAs reported in the literature.

Statistical characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for statistical characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 x 1800 mu m(2).

This paper characterizes experimentally the aging degradation experienced by two different 2.45 GHz power amplifier circuits of similar performance, implemented in a 65 nm CMOS technology. Results demonstrate the importance of the topology selection in order to guarantee robustness against aging effects, and thus the need to predict MOS parameter degradation during the design phase, accounting for the actual DC and RF operation conditions. For that purpose, we propose a semi-empirical compact model that, based on the RMS equivalent voltages at the transistor terminals during circuit operation, can provide an estimation of the aging degradation.

This paper proposes a novel strategy to detect aging in high frequency integrated circuits based on on-line temperature monitoring using built-in differential temperature sensors. To theoretically prove the feasibility of the technique, the paper describes the electro-thermal methodology followed to assert the sensitivity of the temperature sensor's output voltage to track the aging of a 2.4 GHz class A power amplifier.

Differential temperature sensors can be placed in integrated circuits to extract a signature of the power dissipated by the adjacent circuit blocks built in the same silicon die. This review paper first discusses the singularity that differential temperature sensors provide with respect to other sensor topologies, with circuit monitoring being their main application. The paper focuses on the monitoring of radio-frequency analog circuits. The strategies to extract the power signature of the monitored circuit are reviewed, and a list of application examples in the domain of test and characterization is provided. As a practical example, we elaborate the design methodology to conceive, step by step, a differential temperature sensor to monitor the aging degradation in a class-A linear power amplifier working in the 2.4 GHz Industrial Scientific Medical-ISM-band. It is discussed how, for this particular application, a sensor with a temperature resolution of 0.02 K and a high dynamic range is required. A circuit solution for this objective is proposed, as well as recommendations for the dimensions and location of the devices that form the temperature sensor. The paper concludes with a description of a simple procedure to monitor time variability.

Electronic circuits powered at ultra low voltages (500 mV and below) are desirable for their low energy and power consumption. However, RTN (Random Telegraph Noise)-induced threshold voltage variations become very significant at such supply voltages. This paper evaluates the impact of RTN on additional jitter in a ring oscillator. Since FDSOI allows a large range of body bias voltages, this work studies how body biasing affects the oscillation frequency but also the jitter effects. The impact of RTN in NMOS and PMOS devices on frequency as well as the levels of supplementary jitter introduced by RTN are evaluated and compared with classical device noise.

In this work, a CMOS transistor array is presented, which allows performing process variability, Random Telegraph Noise and BTI/CHC aging characterization in a single chip. The array, called ENDURANCE, integrates 3136 MOS transistors, for single and massive electrical testing. This chip, together with a dedicated measurement set-up, allows programming any of these electrical tests, considerably reducing the total time needed for aging measurements by using a parallelization technique.

This paper presents the design of a Broadband CMOS RF Power Amplifier, suitable to be stressed at circuit level but with the possibility to be measured both at circuit and at device level. It allows establishing a relation between the degradation of circuit's RF performances and those of its individual devices parameters. The test structure, measurement set-up and procedure are described in detail.

The dependence of the MOSFET threshold voltage variability on device geometry (width (W) and length (L)) has been studied from experimental data. Our results evidence, in agreement with other works, deviations from the Pelgrom's rule, especially in smaller technologies. TCAD simulations were also performed which further support the experimental data and provide physical information regarding the origin of such deviation. Finally, a new empirical model that assumes different impact of W and L in the device variability has been proposed, which reproduces the experimental results.