In recent years, there has been growing demand to increase the power density in power modules. Therefore, the thermal management of power modules has become more and more critical. In this paper, we show that conventional single-sided power module with wire-bond connection cannot achieve both good steady-state and transient thermal performance under high heat transfer coefficient conditions. The plate-bonded power module has been proposed to resolve this issue. However, the thick copper plate embedded in the power module induces large thermomechanical stress during temperature cycling, leading to poor reliability. To reduce the thermomechanical stress without significantly compromising the thermal performance, a trenched copper plate power module is designed and presented. A parametric study shows that the maximum von Mises stress and plastic strain in the solder layer can be reduced by 18.7%, and 67.8%, respectively, if the single piece of copper plate is replaced by a 3 × 3 trenched copper plate.

Recently, to accurately study the transient thermal behavior of power modules, a transient thermal measurement system was developed to investigate the transient thermal behavior of insulated-gate bipolar transistor (IGBT) modules attached by nanosilver paste and two kinds of lead-free solders. We found that the transient thermal impedance of IGBT modules attached by nanosilver paste was 9% lower than that of the modules using SAC305 and SN100C with 40-ms heating pulse. In addition, finite-element analysis is employed to simulate thermal performance of the IGBT devices. The simulation shows that the transient thermal impedance of IGBT modules attached by nanosilver paste was also lower than that of the modules using lead-free solders. A convenient way was introduced to well predict the transient thermal behavior of IGBT power module. The calculated results agreed well with the measured one. The interface thermal impedance of sintered nanosilver and SNC100C are calculated to be 0.011 ~ 0.031 K/W and 0.022 ~ 0.042 K/W, respectively.

A measurement system for thermal impedance (Z (th)) was developed to evaluate the transient thermal performance of sintered nanoscale silver joints. Five different temperature profiles for low-temperature sintering were evaluated by Z (th) measurements of the joints. The thermal impedance of the sintered samples was altered by the different sintering conditions. Samples that underwent heating profiles with a separate drying stage offered lower thermal impedance than those sintered directly. Exerting pressure of more than 1 MPa during sintering insignificantly improved the thermal impedance. Besides, the impedance could be lowered by extending the holding time of the drying stage and applying pressure as low as 1 MPa during sintering. Characterization of microstructures of the sintered layers was performed by scanning electron microscopy (SEM). With more cracks present, the thermal impedance of the chip joints increased. The presence of cracks was possibly attributed to fast drying or the lack of a drying step.

Since a die-attach layer has a significant impact on the thermal performance of a power module, its quality can be characterized using thermal performance. In this paper, a measurement system for thermal impedance is developed to evaluate three die-attach materials. Thanks to its high temperature sensitivity (10 mV/°C), the gate-emitter voltage of an insulated gate bipolar transistor (IGBT) is used as the temperature-sensitive parameter. The power dissipation in the IGBT remains constant by a feedback loop, regardless of the junction temperature. Experimental results show that the sample using sintered nano-silver for the die-attach has 12.1% lower thermal impedance than the samples using SAC305 and SN100C solders. To check the degradation of the die-attachment, six samples using three die-attach materials were thermally cycled from -40 to 125°C. The experimental results show that, after 500 cycles, the thermal impedance of SAC305 samples and SN100C samples is increased by 12.9% and 13.3%, respectively, which are much higher than that of the sample using the sintered nano-silver for the die-attach (3.1%).

An accurate circuit model for transient behavior is necessary for transient thermal design and coupled electro-thermal simulation of complete power electronics system including semiconductor devices, thermal packages, and heat exchangers. Conventional thermal models of a power module are usually independent of boundary conditions, rendering these models ineffective in predicting the transient temperature of the thermal stacks as a function of heat-transfer coefficients. Thus, the paper presents an RC circuit model in which the thermal resistances and capacitances depend on the material properties and dimensions of the thermal layers, as well as the heat-transfer coefficient of the boundary. Only steady-state FEM simulation is needed to extract the model parameters. The boundary-dependent thermal model has been verified by simulation and experiment, which confirms that it is more accurate than the widely used thermal model based on assumption of 45° heat spreading.

In present electric vehicles (PHEV/HEV/EV), an extra cooling loop is needed to lower the power-electronics coolant temperature below about 65C from the radiator coolant temperature of 105C. One way to reduce the cost of future EVs is to eliminate the extra cooling loop by developing reliable high-temperature power inverter modules that are sufficiently cooled by the radiator coolant. This calls for the development of power packaging technologies that can enable silicon and/or SiC power devices working at junction temperature in excess of 175C. In the current phase of our power packaging research effort, we have focused on replacing the solder-reflow technique for die-attaching power chips by an emerging low-temperature joining technology (LTJT) which involves low-temperature sintering of silver powders. To reduce the process complexity of the conventional LTJT arising from the need of high pressure (30 to 40 MPa or 300 to 400 Kg-force per cm), we used a nanosilver paste material to lower the die-attach temperature below 270C with zero or less than 5 MPa pressure. This simplified LTJT is less likely to damage the chips and allows us to implement a planar packaging scheme for interconnecting both sides of the power devices without using wire bonds. The planar power modules have low parasitic inductances thus less ringing noises from the device-switching action and can be cooled from both sides of the devices for improved thermal management. Details on design and packaging of a double-side cooled power modules and preliminary test results on its electrical performance are presented.

Due to the thin structure used in planar packaging, the electric field intensity within the encapsulation is high, leading to degradation of the dielectric performance. To resolve this issue, a metal posts interconnected parallel plate structure (MPIPPS) is used to reduce the high electric field concentration in the power module. However, the high bonding joint in MPIPPS causes large thermo-mechanical stress within the solder layers. This paper proposes a methodology to optimize the joint height based on a trade-off between the thermo-mechanical performance and dielectric performance of the power module. The impact of the joint height on thermo-mechanical stress and dielectric performance of the module is investigated quantitatively using ANSYS and Maxwell simulations. The results show that using a 0.4mm joint height and Nusil R-2188 encapsulation, the power module can achieve 3 kV breakdown voltage. Experimental results agree with the simulation results.

Due to the thin structure employed in planar packaging, the high electric field intensity may occur inside the power module, leading to degradation of the dielectric performance. To resolve this issue, the Metal-Posts-Interconnected Parallel Plate Structure (MPIPPS) is used to reduce the high field concentration in the power module. However, the high bonding joint in MPIPPS will cause high thermo-mechanical stress in the solder layers. In this paper, a methodology to optimize the joint height based on the trade-off between thermo-mechanical performance and dielectric performance of the power module is proposed. The impact of the joint height on thermo-mechanical stress and dielectric performance of the module is investigated quantitatively using ANSYS and Maxwell simulations. The results show that with 0.4 mm joint height and Nusil R-2188 encapsulation, the power module can achieve 3 kV breakdown voltage. The experimental results agree with the simulation results.

This paper investigates the impact of the geometry of the heat spreader and the heat transfer coefficient of the heat exchanger on the steady-state and transient thermal performances of power semiconductor modules. Results show that the steady-state thermal resistances along the thermal flow path change with heat transfer coefficients owing to limited heat spreading effect. The transient thermal performance is mainly affected by the thermal capacitance in the power module. To minimize the transient thermal impedance without sacrificing weight, cost, and so on, the thickness of the heat-spreader should be selected to match the thermal time constant to the transient duration. Based on these results, a methodology is proposed to conservatively select the thickness of the heat spreader to maintain the silicon junction at a required peak transient temperature. The methodology is exemplified and verified by a thermal design for a medium-voltage power module.

Voltage regulator modules (VRM) have stringent efficiency and transient response requirements. A stepping inductance based VRM (SI_VRM) has been proposed by other researchers with the aim of achieving fast dynamic current response under step-load conditions. However, the scheme proposed to control the SI_VRM has several problems, such as high voltage ripple under 'inductor current recovery' condition and interruption of inductor current without any freewheeling action. In this paper, a new control scheme is proposed for the SI_VRM which can achieve fast transient response, smooth transition between different operating states, low ripple voltage both under normal and inductor current recovery conditions. The paper also investigates the requirements of the stepping inductance and its design. Simulation and experimental results are provided to confirm the expected improvements in performance