For high-capacity applications, paralleling multiple silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) is essential. However, it is challenging to achieve complete symmetry in the gate circuits of parallel devices, resulting in mismatched gate inductances, which may lead to the current imbalance. This article focuses on investigating the evolution of threshold voltage dispersity under mismatched gate inductances and its impact on the current sharing evolution. It is found that mismatched gate inductances cause the threshold voltage dispersity to increase with gate stress time, thereby inducing a deterioration in current sharing. A boost converter with two devices in parallel was tested, demonstrating that the difference in the minimum turn-off gate voltage including undershoot is the primary trigger for increased threshold voltage dispersity. Besides, an off-state gate voltage optimization strategy was proposed to effectively mitigate the increase in threshold voltage dispersity and improve the evolution of current sharing under mismatched gate loop inductances. The findings are intended to improve the performance of SiC MOSFETs in parallel applications.

The third quadrant (3rd-quad) of SiC MOSFETs is typically used for deadtime freewheeling, which improves the power density. Because the channel in the 3rd-quad may not be completely closed, the 3rd-quad characteristics are more or less influenced by threshold voltage drift. However, a comprehensive evaluation of the impact of threshold drift on the 3rd-quad characteristics remains to be completed. In this article, the effects of threshold drift on 3rd-quad characteristics are revealed, and the mechanisms behind the effects are discussed. The sensitivity of static and dynamic 3rd-quad characteristics to threshold voltage are studied under different off-state gate voltage, temperature, and p-base region resistance. Moreover, the explanation for the difference in sensitivity between devices is analyzed. The research provides guidance for both the application and chip design of SiC MOSFETs.

The inherent limitation of threshold voltage drift in silicon carbide metal-oxide-semiconductor field-effect transistors has restricted their broader applicability. This paper proposes a driving method that introduces an additional gate drive level, effectively reducing the threshold voltage drift in silicon carbide metal-oxide-semiconductor field-effect transistors while preserving the advantages of a negative gate turn-off voltage. The practical effectiveness of this method is validated through experiments.

Parallel connection of silicon carbide (SiC) metal oxide semiconductor field effect transistors (mosfets) is an efficient solution for high-capacity power converters. However, a more or less dispersity of the parallel chip parameters is inevitable, which may lead to the current imbalance. Due to the existence of dynamic threshold voltage drift, the dispersity of the threshold voltage of the parallel devices during the whole life is vital for the long-term reliability. This article aims to investigate how dispersity evolves and how it affects the current sharing. It is found that the threshold voltage dispersity indeed does not keep constant during the operation, but on the opposite, it increases with gate stress time, especially at elevated temperatures. This leads to the deterioration of the current sharing of parallel devices. A boost converter with two devices paralleled was built and tested, which validated that the threshold voltage dispersity and current imbalance ratio increase with stress time. Finally, a classification method is proposed to suppress the increase in threshold voltage dispersity and current imbalance ratio. These findings are believed to be useful to improve the performance of SiC mosfets in parallel applications.

The threshold voltage instability of silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETS) has drawn extensive attention. However, there is limited research on the recovery performance of the threshold voltage of SiC MOSFETS. In this article, the performance and the physical mechanism of the threshold voltage recovery have been studied with experiments and simulations. It is found that no more than 0.25-V short-term recovery of the threshold voltage can be observed within 1 h after the gate bias. Furthermore, the threshold voltage drift can undergo a more complete long-term recovery even exceeding 75% of the dynamic threshold voltage drift with higher recovery temperature and more negative gate bias. The findings are intended for better understanding and management of potential threshold voltage drift in device tests and applications.

Modular multilevel converters (MMCs) are widely used in grid scale power electronics. Due to the presence of a dc component in the arm current, the MMC submodules (SMs) show an unbalanced current loading profile. This may lead to some semiconductor chips being more stressed than others, significantly affecting the overall reliability. To level the junction temperatures and improve the SM reliability, this article proposes an asymmetrical power module design in line with the loading profile, allocating more chips to higher current parts. This is shown to be realistic if the power flow is unidirectional. The concept is investigated using simulation backed by experiment. It is shown that the designed power module can significantly reduce the maximum temperature and the total power loss can be reduced by 5%–8%. The chip utilization rate is also improved. The proposed module is applicable in a certain range of power factor and modulation index adjustment. This article provides a guidance for optimum design of the power module for the SMs in an MMC.

Owing to the superior performances, silicon carbide (SiC) metal oxide semiconductor field effect transistors ( mosfet s) attract a lot of attention. To increase the power density, it is desired to use the third quadrant (3rd-quad) characteristics of the mosfet rather than the externally paralleled Schottky diode for freewheeling during the deadtime. It has been known that the 3rd-quad is far more than a body diode, and the MOS channel is also an important part of it. The channel may be not fully closed and, therefore, play a significant role in the reverse conduction even when the gate is zero or negatively biased. However, a comprehensive study of the 3rd-quad characteristics is still to be conducted. In this article, experiments and simulations are conducted and a physical model is developed to explain the 3rd-quad characteristics of the SiC mosfet . It reveals how and why the 3rd-quad characteristics are affected by the gate voltage and the junction temperature. This article is helpful for not only the application of SiC mosfet but also the device design.

In modular multilevel converter (MMC) systems, it’s important to improve the effectiveness and dependability of power semiconductor devices. In order to improve the chip utilization and lower the peak junction temperature, based on the practical upper and lower bridge arms current, the asymmetrical press-pack IGBT devices were proposed. In this paper, the current of the upper and lower bridge arms of the sub-module is obtained through simulation, and the actual power losses of the IGBT and anti-parallel FRDs under practical operation are calculated. Then the power losses are imported into the finite element simulation, and the peak junction temperature and temperature distribution of proposed asymmetrical press-pack IGBT modules were analyzed. The results show that the proposed asymmetrical press-pack IGBT structure not only improve the chip utilization, but also lower the peak junction temperature. This contributes to the reliability of the MMC system.

Parallel devices in nonuniform conditions can easily lead to reduced overall reliability or even failure due to uneven energy distribution. Especially under long-term avalanche stresses, the degradation of the device may have a great impact on the electrical parameters and performance. To study the degradation tendency and aging mechanism of parallel-connected silicon carbide (SiC) MOSFET, the repetitive unclamped inductive switching (UIS) experiments are carried out in this article. Technology computer-aided design (TCAD) simulations are utilized to simulate the temperature change and current distribution of the chip during an avalanche. The results showed that for planar and trench devices, the electrical parameters drifts are different during repetitive avalanches. The degradation rates are unequal for parallel devices with different case temperatures. Two degradation mechanisms, including hot holes injection and trapping in the gate oxide and metal aging, are found to dominate in the repetitive avalanche process. The findings are helpful for better understanding of degradations for parallel repetitive avalanches in device applications.

With increasing applications of silicon carbide power MOSFETs, more attention is being paid to reliability issues, among which the long-term stability of the gate threshold voltage is of paramount importance. In this article, laboratory experiments are conducted to investigate the threshold voltage instability under ac gate stresses with different duty ratios, and on and off-state gate voltages. It is found that no prominent drift would occur even for bipolar gate stresses, as long as the off-state gate voltage is within (higher than) the critical negative bias voltage which is related to the device fabrication process. Furthermore, not only the gate voltage swing but also the gate voltage polarity will affect the speed of threshold voltage drift when it occurs. The findings are intended for better understanding and management of potential threshold voltage drift in device applications.

Silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) are regarded as the key device for the next generation of power electronics. However, wide applications are hindered by the threshold voltage instability. How the threshold voltage drifts under both static and dynamic gate stress has been reported. But the underpinning mechanism remains to be revealed, which is the basis of the exploration of the application solutions. This letter is to investigate why the threshold voltage drifts. It is found that the local electric field plays the key role behind the threshold instability, which is a function of dV GS / dt . Based on that, a physical model is proposed and experimentally verified. These findings provide not only a way to understand the mechanism but also a hint of how to mitigate the threshold instability by active gating in power electronics applications.

A comparative study on SiC MOSFETs is carried out with an emphasis on the design of integrated Schottky barrier diode (SBD) with numerical simulations by Sentaurus TCAD. Compared with the conventional SiC MOSFET (C-MOS) and the conventional SBD-embedded SiC MOSFET (C-MOSBD), the MOSFET (M-MOSBD) features a hybrid doping mesa above the JFET region where a Schottky contact is formed, which exhibits a superior trade-off between the on-state resistance ( R dson ) and the reverse transfer capacitance ( C rss ). Besides, the integrated diode in M-MOSBD renders a better trade-off between OFF-state junction field ( E Smax ) and forward voltage ( V F ) when compared to C-MOSBD and the conventional junction barrier Schottky diode (JBS), i.e., the external SBD of C-MOS. In the double pulse test simulation, C-MOS exhibited the largest switch loss followed by C-MOSBD, and M-MOSBD is the smallest. Therefore, in power switching applications where reverse conduction is required, M-MOSBD greatly reduces the chip area while presenting better characteristics.

The conduction characteristics of the third quadrant of SiC MOSFET include the current distribution of the body diode and the MOS channel, which are sensitive to many factors. In this paper, the influence of dynamic threshold voltage drift on third quadrant characteristics of SiC MOSFET is studied. By combining the equivalent potential model, TCAD simulation, and experiment, it is revealed that once the threshold voltage drifts under dynamic gate voltage stress, the static and dynamic characteristics of the third quadrant of SiC MOSFET will change. Furthermore, the current sharing of parallel devices is also affected by dynamic threshold voltage drift. These results provide an effective guide for the third quadrant application of SiC MOSFET.

Silicon carbide (SiC) power MOSFETs are gradually being put into the market due to their superior performance, and their threshold voltage instability issues during long-term operation attract electrical engineer's attention. In this conference, the threshold voltage drift caused by the long-term dynamic gate stress at room temperature and high temperature is investigated. Besides, the effects of dynamic gate stress with different duty cycles on the threshold voltage drift are experimentally studied. It is found that a more negative threshold voltage drift is observed at high temperatures compared with the drift at room temperature. Moreover, the duty cycle only affects the dynamic threshold voltage drift in the range of 0 to 5% and 95% to 100%. These results help to understand the causes and characteristics of the dynamic threshold voltage drift.

The voltage spikes generated by the turn-off of the high-speed switches can easily drive the devices into an avalanche mode and even failure. In order to study the silicon carbide (SiC) MOSFET's avalanche limit of a single device and the influence of electrical parameters of paralleled devices, an unclamped inductance switching (UIS) test platform for single and paralleled SiC MOSFETs is set up. This paper summarizes the single-pulse avalanche limit of single MOSFET under different inductances and different temperatures through experiments. In addition, the characteristics of parallel connected MOSFETs under different electrical parameters are also analyzed, and the main factors that affect the avalanche failure are shown.

A SiC/Si hybrid switch (HyS) composed of a larger current IGBT and a smaller current MOSFET can provide higher cost performance. Previous research on the hybrid switch mostly focuses on reducing loss and balancing junction temperature through different control strategies, neglecting the reliability issue caused by the load current exceeding the safe operating area (SOA) of SiC MOSFET with a lower current rating. In addition, it remains an unsolved issue that how to design gate resistances for a Si/SiC HyS. This manuscript investigates the impact of gate resistances on switching-on behaviors of a Si/SiC HyS in a double pulse test. Furthermore, the tradeoff between switching loss and the device reliability can be used as a reference for selecting the switching-on gate resistance of a hybrid switch.

For silicon carbide (SiC) power MOSFETs, threshold voltage drift is a remaining obstacle in their way to the market. This study experimentally investigates the drift under dynamic or switching gate stresses. It is shown that, beside static stress, the switching events can themselves be a driving force of the threshold voltage drift. However, this happens only when the dynamic gate stress is bipolar. The study extends to show that the dynamic stress induced drift can be sustained. The findings can be used in further work for managing and coping with the threshold voltage drift in device applications.