The forward gated-diode method is used in this paper to extract the dielectric oxide thickness and body doping concentration of nano-scale MOSFETs, especially when both of the variables are unknown previously. Firstly the dielectric oxide thickness and the body doping concentration as a function of forward gated-diode peak recombination-generation (R-G) current is derived from the device physics. And then the peak R-G current characteristics of the MOSFETs with different dielectric oxide thicknesses and body doping concentrations are simulated with ISE-Dessis for parameter extraction. The results from the simulation data demonstrate an excellent agreement with those extracted from the forward gated-diode method.

Characteristic variation of FinFET due to Fin vertical nonuniformity is simulated in this paper, based on the compact device model. This vertical nonuniformity is generated during the real etching process and induces Fin thickness variation along the height direction. Therefore, the characteristics, such as threshold voltage, sub-threshold slope, on state current, off state current and total channel resistor are investigated influenced by Fin height and deviation angle. The impact of the deviation angle on both digital and analog circuit performance is also predicted.

The random dopant fluctuation (RDF) of double gate (DG) MOSFET based 6-T SRAM is investigated with three-dimensional (3-D) statistical simulation. The doping profile is generated by matlab and the threshold voltage variation due to RDF is obtained by device simulation. Then the performance of DG MOSFET based 6-T SRAM is evaluated by feeding the results into a compact DG MOSFET model using HSPICE Monte Carlo simulation. The results show that pull down transistor dominates static noise margin (SNM) fluctuation and access transistor dominates write margin (WM) fluctuation.

In this paper, an accurate method is used to extract and separate interface and gate oxide traps by the subthreshold current of MOSFET. The xide trap is supposed to result in a turn-on voltage shift in the semi-log plotted transfer characteristics, while interface trap influences subthreshold slope of the device. The above theory is verified by ISE-Dessis simulation. The results demonstrate that this method is effective and accurate for extracting parameters of devices with gate length less than 1 mu m.

>The forward gated-diode method is used to extract the dielectric oxide thickness and body doping concentration of MOSFETs,especially when both of the variables are unknown previously.First,the dielectric oxide thickness and the body doping concentration as a function of forward gated-diode peak recombination-generation (R-G) current are derived from the device physics.Then the peak R-G current characteristics of the MOSFETs with different dielectric oxide thicknesses and body doping concentrations are simulated with ISE-Dessis for parameter extraction.The results from the simulation data demonstrate excellent agreement with those extracted from the forward gated-diode method.

A physical based model for predicting the performance degradation of the FinFET is developed accounting for the interface state distribution effect due to hot carrier injection (HCI). The non-uniform distribution of interface state along the FinFET channel is first extracted by a forward gated-diode method and then reproduced by an empirical model. From this, a physical-based device model, which accounts for the interface state distribution effect, is developed to predict the performance degradation of FinFET. The result shows that the developed model not only matches well with the experimental data of FinFET in all operation regions, but also predicts the asymmetric degradation of saturation drain current in forward and reverse operation mode. Finally, the impact of HCI to a 6-T SRAM cell is simulated using HSPICE.

In this paper, the forward gated-diode method is used to extract the gate oxide thickness and doping concentration of MOS device simultaneously. The gate oxide thickness and body doping concentration are first extracted from the recombination-generation (R-G) current, and then from the simulation result of ISE-Dessis. The results obtained from R-G method shows a good agreement with the simulation data.

Temperature dependence of the interface state distribution due to hot carrier injection (HCI) effect in FinFET device is investigated in this paper. The interface state distribution along the FinFET channel at various temperatures is first extracted by measuring the generation–recombination (G–R) current and then the shift of interface state density with temperature is analyzed. The result shows that the density of interface states increases with elevating temperature from 28 °C to 128 °C. While the change of generation rate slows down with rising temperature and the distribution region is insensitive to both stress time and temperature. Based on the measured data, an empirical Gaussian-like model is proposed to describe the interface state distribution along the FinFET channel and good agreements with experimental data are obtained.

This paper proposed an advanced logarithm cofactor difference operator (LogCDO) method to extract parameters of the MOS devices' post-breakdown current. The experimental results of the post breakdown current in MOS devices at different temperature are used to demonstrate the validity of the advanced LogCDO method. The post-breakdown current is equivalent to a dual diode circuit model, and then the LogCDO method is applied to extract key model parameters. The extraction results are consistent very well with the measured data over a wide range of temperature.

This paper presents the asymmetric issue of FinFET device after hot carrier injection (HCI) effect and impact on the digital and analog circuits. The interface state distribution along the FinFET channel is first extracted from hot carrier injection experimental data, and then develops a compact FinFET model to simulate the impact on asymmetric distribution of interface states to the device characteristics. The results show that the asymmetric degradation is much more significant in Ids-Vds characteristics than in Ids-Vgs characteristics. On the other hand, digital and analogy circuits exhibit different asymmetric performance degradation in various operation cases.

This paper describes a web-based platform for nanoscale non-classical device modeling and circuit simulation, especially for non-classical CMOS device compact modeling and circuit performance prediction. This platform is based on program libraries, including model code files. We use SPICE as circuit simulation framework, and the Verilog-A as model design language. Based on the user input deck content, running embedding device and circuit programs, the platform produces several types of device characteristics output such as data texts and graphs on the web page for analysis, according to the simulation results and users' requests. Some nanoscale device modeling examples and the circuit simulation cases are demonstrated by the means of the platform configures and function application. It is shown that not only does this kind of platform address problems arising from the dependence on computer operating system of modeling and simulation software, the complexity of software and program update, but also helps researchers focus on their research on device physics and circuit design, display their research results and share latest research achievements or new technology online, which will accelerate the development of device modeling and circuit design technology in turn.

We have studied the formation of a high-quality LaALO(3) (LAO) film directly on silicon substrates by the pulsed laser deposition method as a novel high-k gate dielectric. The LAO films can remain amorphous at temperatures up to 850degreesC. An atomic force microscopy study indicated a very smooth surface of the deposited films with a rms of 0.14 nm for an 8 nm LAO film. The structures and electrical properties of metal-dielectric-semiconductor (Pt/LAO/Si) capacitors were investigated with LAO films deposited under different ambient conditions. High-resolution transmission electron microscopy indicated that interfacial reactions often occur for films of LAO deposited under oxygen ambient. A small effective oxide thickness of 1.2 nm was obtained for those films deposited under 20 Pa nitrogen ambient, with the corresponding leakage current density 17.1 mA cm(-2) at +1 V gate voltage. It is proposed that amorphous LAO films are a novel promising alternative high-k gate dielectric material in future ultra-large scale integrated devices.