The limited interfacial adhesion of photosensitive dielectric materials poses a critical challenge to the reliability of advanced packaging substrates, particularly for ultra-fine line fabrication. However, their curing behavior is complex and poorly understood, hindering effective control of interfacial adhesion. Herein, the thermal curing behavior of a commercial photosensitive dielectric build-up film (PVF) after photo curing was analyzed using non-isothermal differential scanning calorimetry (DSC) based on nth-order and autocatalytic models, and the adhesion strength between copper and PVF was evaluated by tuning the curing behavior. DSC results show that PVF exhibits two overlapping exothermic peaks, and both reactions follow autocatalytic kinetics. A quantitative correlation between curing behavior and interfacial adhesion was established. The Cu–PVF adhesion strength initially increased and then decreased as the curing time extends from 60 to 100 min at 180 °C. This behavior was attributed to curing-induced structural evolution, which regulated interfacial morphology and mechanical interlocking, providing a practical strategy to improve interfacial reliability.
To accurately characterize the strength of ultrathin bilayer semiconductor dies, this study proposes a detailed analytical model for the four-point bending test, incorporating large deflection kinematics and interfacial friction. By utilizing Legendre-Jacobi's elliptic integrals strictly within the real domain, the analytical formulation overcomes the mathematical singularities of previous complex-valued methods, offering markedly improved computational efficiency while remaining mathematically equivalent to the earlier approach. The framework is further generalized to account for a nonzero net axial force arising from support friction, revealing a previously undocumented curvature discontinuity at the loading support that persists even without friction. The model is validated through finite element simulations and experimental measurements across a range of die thicknesses, film thicknesses, support spans, and friction conditions. A key finding reveals a non-uniform stress distribution, with the maximum bending stress localized at the mid-span rather than uniformly distributed as assumed by classical theory. This peak stress deviates from the classical linear prediction by up to 21%, depending on specimen geometry, causing classical linear models to misestimate the actual failure probability by up to several-fold in weakest-link reliability assessments for typical silicon dies. This comprehensive theoretical model provides an important and accurate tool for optimizing the mechanical reliability of next-generation ultrathin packages.
This study investigates the drift and recovery behaviors of threshold voltage (Vth) and ON-resistance (Ron) in 650 V Schottky p-GaN gate HEMTs under repetitive short-circuit (SC) stress. Experimental results show that the repetitive SC stresses with bus voltage (Vdc) of 200 V and 300 V produce significantly different effects on both Vth and Ron. Under the repetitive SC stress with Vdc = 200 V, Vth gradually shifts positively and then saturates, while Ron gradually shifts negatively and then saturates. After stress, Vth exhibits full recovery and Ron also can recover to its fresh value. In contrast, under the repetitive SC stress with Vdc = 300 V, Vth exhibits a smaller positive shift and faster saturation, while Ron shows a smaller negative shift and faster saturation. After stress, Vth displays an over-recovery and a longer recovery time, but Ron fails to fully recover. Furthermore, TCAD-based electrical and thermal simulations are carried out to reveal the different effects of the two Vdc levels on the Vth and Ron. Specifically, compared to Vdc = 200 V, a higher Vdc of 300 V evidently increase the electric field intensity in the p-GaN gate region and the access region near the drain edge, as well as a higher temperature in the narrow channel region beneath the field plate, extending toward the drain and buffer layer. These results provide valuable insights into the repetitive SC degradation behavior of 650 V p-GaN gate HEMTs, highlighting the critical role of the drain-side electric field distribution in device reliability.
This work reports a novel p-AlGaN HEMT architecture incorporating a low-Al-content step-graded buffer layer (LAC-HEMT) to enhance radiation hardness. By replacing a portion of the source side GaN buffer with AlGaN steps featuring low Al mole fractions from 0.01 to 0.03, the polarization-induced interface charge distribution is effectively modulated. This modulation not only redistributes the internal electric field to suppress excessive carrier accumulation but also enhances carrier transport control. Furthermore, the stepped buffer architecture mitigates lateral electric-field crowding, ultimately reducing impact ionization. Through systematic multi parameter optimization, the optimal structural configuration is determined to be N = 2, x = 0.01, and L = 100 nm, where N denotes the number of steps, x represents the Al composition of the stepped AlGaN layer, and L is the distance between the step-graded buffer and the AlGaN barrier layer. Simulation results demonstrate that the LAC-HEMT significantly outperforms the conventional device (C-HEMT). The breakdown voltage (VBR) increases from 696 V to 1303 V, while the single event burnout threshold voltage (VSEB) escalates from 290 V to 1130 V, corresponding to improvements of 87.2% and 289.6%, respectively. This architecture provides a viable and process compatible approach for developing high reliability GaN power electronics.
In this work, a detailed investigation is carried out to assess the impact of interface trap states on digital, analog, and RF characteristics of a Junctionless (JL) T-shaped Nanosheet FET. The concentration of donor and acceptor trap states is varied from 2 × 1012 cm−2 to 8 × 1012 cm−2. The results reveal that acceptor traps predominantly deteriorate the channel inversion capability, leading to reduced on-state current (ION), enhanced subthreshold characteristics, and lower output conductance. In contrast, donor traps act as electron-supplying centers, elevating both the ION and off-state currents (IOFF) while degrading subthreshold swing (SS) and short-channel immunity. The influence of trap polarity becomes prominent in analog and RF figures of merit, where donor-induced conduction enhancement causes higher gate capacitance, reduced transconductance efficiency, and elevated output conductance. Meanwhile, acceptor traps exhibit a peak behavior in both transconductance (gm) and CGG due to the progressive filling of negatively charged states with increasing gate bias. The donor traps at 8 × 1012 cm−2 exhibit minimal intrinsic delay of ∼0.8 ps. The impact of interface traps on Common Source (CS) amplifier analysis revealed the superiority of higher acceptor trap concentrations in improving the amplification (∼5.99) capability of analog circuit performance.
Pulsed laser microstructuring is widely used in silicon processing, but its influence on the electrostatic state of nearby dielectric–semiconductor interfaces remains insufficiently understood before catastrophic laser-induced damage. Here, we investigate the local and near-spot electrostatic response of thermally oxidized SiO2/Si MOS structures subjected to defocused 1062-nm nanosecond laser irradiation. n-Si(111) samples with a 150-nm thermal oxide layer were irradiated to produce approximately circular laser-modified regions with diameters of 0.9–1.2 mm, and high-frequency capacitance–voltage (CV) measurements were performed using an InGa top contact. The reference-voltage shift was extracted at a fixed normalized capacitance level (C/Cmax=0.45) and expressed as a charge-equivalent electrostatic shift metric, rather than as an absolute oxide- or interface-charge density. Repeated evaluations on four independent MOS samples show that the local response evolves non-monotonically within the 0–50 s pre-catastrophic exposure window. At fixed average power and exposure time, the response also depends on the coupled pulse-train condition, including repetition rate, pulse energy, and accumulated pulse number. Near-spot measurements performed 1–2 mm from the irradiated edge indicate a weaker electrostatic perturbation outside the visibly modified region. Together with the observed slip-line/deformation morphology and first-order thermal considerations, these results are consistent with a substrate-mediated contribution to the oxide/interface electrostatic response. These findings provide an experimentally supported phenomenological basis for identifying low-electrostatic-perturbation pre-catastrophic processing windows in laser-assisted silicon microfabrication, while long-term dielectric integrity requires further verification by leakage-current, dielectric-breakdown, recovery, and bias-temperature-stress measurements.
This work investigates the influence of gate metal selection on the gate leakage current of AlGaN/GaN high-electron-mobility transistors (HEMTs) through a systematic temperature-dependent analysis in the range of 238.5–473.15 K. A direct comparison between different gate-metal/process configurations characterized under the same measurement conditions is performed to clarify their impact on leakage mechanisms. The results reveal a transition between dominant conduction mechanisms as a function of temperature, electric field, and gate stack properties. At low temperatures and electric fields, the leakage current is mainly governed by tunneling-related processes, while thermally activated mechanisms become increasingly significant as temperature increases. Under high electric field conditions, the observed trend is consistent with Fowler–Nordheim tunneling. A semi-logarithmic analysis of ln (IG) as a function of inverse temperature shows the absence of a well-defined Arrhenius behavior, indicating that the leakage current is not dominated by a single thermally activated mechanism. Instead, the weak temperature dependence observed in several regimes suggests a strong contribution of tunneling-related transport, with additional mechanisms becoming relevant depending on the device structure and bias conditions. The results demonstrate that the transition between conduction mechanisms occurs over different temperature ranges depending on the gate metal, highlighting the critical role of the metal–semiconductor interface in defining leakage behavior. These findings provide improved insight into leakage mechanisms in GaN-based devices and offer guidance for device design and reliability optimization.
This study firstly presents a numerical investigation into the effects of anisotropic behaviors on the drop impact reliability of Sn-rich solder joints in a system in package through finite element simulation. Our established anisotropic constitutive model is employed in the simulation model. We analyze the failure-prone locations via the distribution of von Mises stress and evaluate the reliability through the equivalent inelastic strain. The results show that solder joints with their c-axial aligned parallel to the impact direction exhibit significantly lower accumulated inelastic strain compared to those with an a-axial alignment. Serving as a comparative surrogate metric for crack initiation driving force, this pronounced strain disparity reveals that the c-axial alignment yields superior reliability. This work highlights the necessity of incorporating anisotropy in drop impact reliability modeling and process window design of Sn-rich solder joints, which, when combined with statistical microstructural characterization, could assist in interpreting the reliability variation observed in mass production.
This paper presents a novel in-situ monitoring approach for assessing bond wire aging in IGBT modules, utilizing the maximum turn-on voltage of auxiliary emitter (VeE-max) as an aging-sensitive indicator. Initially, based on the turn-on characteristics of IGBT module and equivalent circuit model, this paper systematically analyzes the physical origin and evolution mechanism of VeE-max in relation to bond wire aging. To facilitate real-time measurement, a dedicated peak monitoring circuit is designed and implemented. Then, the feasibility of the proposed method is verified using a double-pulse test circuit, and the effects of operating conditions such as bus voltage, gate resistance, load current and junction temperature are discussed. Experimental results demonstrate that VeE-max exhibits high sensitivity to bond wire aging, with a measured variation of approximately 1.795 V per wire and is not affected by junction temperature and load current, validating its effectiveness as a condition monitoring parameter.
The aluminum-silicon (SiAl) interface mechanical property is of decisive importance to the thermal endurance and operation lifetime of insulated gate bipolar transistor (IGBT) modules, since the primary mechanism for interfacial mechanical degradation is silicon segregation at grain boundaries. The molecular dynamics (MD) simulations on quantifying the impact from the Si segregation on the interface fracture behavior of the SiAl interfacial under uniaxial compression. The higher Si segregation critical strain energy release rate (Gc) and fracture toughness (Kc) by 20–35%, suggesting complex tradeoff between stiffness and toughness. When there is pre-existing crack, the maximum tensile stress (σmax) decreased by 25%, which shows much weakened load carrying capability. The interfacial mechanical characteristics are sensitive to the thickness of Si layer in the non-monotonic way and an optimal value can be found within the range of 30–33 Å. The above results give atomic-scale understanding of SiAl interface degradation physics and serve as reference for materials design of more reliable IGBT devices.
High-power operation represents the most common and challenging condition for photovoltaic (PV) inverters, where the distribution of power losses and thermal management directly influence system efficiency and long-term reliability. Aiming at the high thermal stress and overheating risk of PV inverters during high-power operation, an online loss assessment method based on a local linearization model was developed. According to the proposed approach, a linear relationship between output power, losses, and steady-state temperature rise was established, and a thermal resistance disturbance model was introduced to adapt the model to changes in cooling performance. The method was validated using experimental data and finite element simulation results from a 1.1 MW centralized PV inverter under different air duct health conditions. Experimental results show that the method can accurately estimate the main heat source losses in the high-power range, and under degraded cooling conditions, the temperature rise estimation error remains within ±5 °C. Compared with conventional models, the proposed method has a lower computational cost, is suitable for online monitoring, and can adapt automatically to cooling performance variations, thus providing an efficient and reliable solution to improve the long-term stability and energy efficiency of PV inverters.
Wafer-to-wafer (W2W) direct bonding has garnered extensive attention in next-generation 3D IC packages due to its remarkable capability to reduce interconnect pitch and thereby enhance device performance and integration density. However, deformation mismatches between the top and bottom wafers during the bonding can introduce post-bonding distortion, which further limits the device performance. This work uses a finite element analysis model to simulate the W2W bonding process and post-bonding in-plane distortion. A new adhesion model is employed to characterize the interaction force between wafers, which significantly improves computational efficiency. Through the simulation and experimental approaches, the bonding dynamics and wafer deformation are assessed for various top wafer release and piston force scenarios. The results confirm that delayed release of top chuck vacuum would increase stress in the top wafer, while appropriately optimized piston force effectively mitigates the local distortion residual near the wafer center. The proposed simulation model realizes high-reliability prediction of the bonding dynamics process as well as the post bonding in-plane distortion. This can provide important guidelines for optimizing the bonding process recipes.
Controlling interfacial reactions and thermal degradation during laser-assisted bonding (LAB) is critical for ensuring the long-term reliability of advanced electronic packaging. Owing to its highly localized heating and reduced thermal impact on surrounding components, LAB has attracted considerable attention as a promising joining technique for electronic packaging applications. However, the effects of laser bonding time on interfacial microstructure evolution and long-term reliability have not yet been fully clarified. This study investigated the effects of laser bonding time on interfacial reactions, IMC growth behavior, and the mechanical reliability of Sn-3.0Ag-0.5Cu/Cu solder joints. SAC305 joints were fabricated with bonding times ranging from 1.2 to 2.0 s and subsequently subjected to isothermal aging at 100, 125, and 150 °C for durations of up to 1000 h. In the as-reflow condition, the interfacial Cu6Sn5 morphology exhibited a clear morphological transition from scallop-type to prism-type structures with increasing bonding time. During isothermal aging, IMC growth was dominated by Cu6Sn5 thickening at 100 °C, whereas accelerated Cu6Sn5 coarsening and the formation of a continuous Cu3Sn layer were observed at higher temperatures, accompanied by Kirkendall void formation. Arrhenius analysis confirmed diffusion-controlled IMC growth, with activation energies ranging from 73.7 to 52.4 kJ mol−1 depending on bonding time. Longer bonding times were associated with higher IMC growth rate constants and lower activation energies. High-speed shear testing at 2 m/s revealed progressive degradation of joint strength and a transition in fracture mode from ductile to interface-dominated brittle fracture with increasing aging temperature. These results demonstrate that optimization of laser bonding time is critical for balancing interfacial stability and long-term reliability in SAC305 solder joints. Within the present experimental conditions, a bonding time range of approximately 1.2–1.4 s provided a balanced combination of stable initial bonding and suppressed interfacial degradation during long-term aging test.
Based on three mainstream failure localization techniques—Emission Microscopy (EMMI), Optical Beam Induced Resistance Change (OBIRCH), and Infrared Thermography (THERMAL)—this paper proposes a microscopic photothermal distribution testing system. This system employs a bilinear interpolation algorithm to magnify images by four times, achieving an effective pixel pitch approaching 5 μm when using a 20 μm-level macro lens, which is one of the key advantages for reducing the cost. By overlaying and registering visible-light images with microscopic infrared thermographs, and incorporating a voltage-step hot spot tracking strategy, the system can rapidly pinpoint the defective region within a large area. Subsequently, a Focused Ion Beam Dual-Beam Scanning Electron Microscope (FIB-SEM) is used for precise cross-sectional preparation and microscopic analysis, forming a complete workflow for chip leakage localization and failure mechanism analysis. When applied to actual failure cases, this approach successfully located the failure points with precision and identified their root causes, providing clear direction for product improvement and process optimization.
