This paper reviews the development of germanium technology for applications in high performance CMOS ICs, rf and MMICs. The paper covers the development of MOSFET technology with respect to source/drain doping and gate dielectrics. Germanium has higher junction leakage currents than silicon on account of its lower energy bandgap. It is a scarce material, expensive and the wafer size is limited. To minimize these disadvantages germanium will be employed as a thin layer on an insulator substrate. Various methods of producing germanium-on-insulator (GeOI) substrates are outlined. These include the Smart-cut process, the condensation process starting with SOI wafers and the epitaxial growth of germanium on lattice matched crystalline oxides grown on silicon substrates. Partial GeOI layer techniques reviewed are dislocation necking of solid phase epitaxial layers grown in narrow high aspect ratio trenches and liquid phase epitaxy from rapid melt germanium confined in micro-crucibles. The fabrication of germanium on dielectric substrates such as quartz, sapphire and alumina are also discussed.

Germanium (Ge) has been bonded to fine grain alumina (Al2O3) by means of a polished polycrystalline silicon interface layer. After room temperature bonding and subsequent bond strength annealing at 150 oC for 24 hrs, the germanium layer was ground and polished to 100µm. Low temperature Tungsten (W) gate circular geometry devices, W/L = 9, fabricated on this layer exhibited effective mobility values of 150 cm2/Vs. This is much lower than results obtained on equivalent devices on bulk Ge. Improvement in the germanium polish process resulted in transistors with an effective mobility of 415 cm2/Vs, comparable to that of the bulk Ge devices. Low temperature measurement, down to temperatures of 173 K, showed an improvement in device performance resulting in both an increase in effective mobility to 591 cm2/Vs and a decrease in sub threshold slope from 180 mV/dec to 60 mV/dec indicating a reduction in leakage current.

Tungsten gate germanium MOS transistors have been manufactured on bulk germanium platforms. Hole mobility in the range 450 cm2/Vs has been achieved on bulk germanium, but mobility is reduced during the densification of thinner dielectrics at 600C. This may be due to the formation of volatile GeO at the interface during densification. Low temperature measurements of the thinner dielectric device indicate that lattice scattering is dominant at room temperature for the device where the densification was omitted and the excellent subthreshold slopes at low temperatures also indicate devices of good quality.

Al2O3 and HfO2 films were deposited on germanium substrates by atomic layer deposition (ALD) and analyzed by MOS capacitor electrical characterization. In-situ plasma nitridation performed prior to ALD was found to improve the stability of the interface. For Al2O3/GeON/Ge capacitors, a 450°C anneal in nitrogen ambient reduced hysteresis and oxide fixed charge to 90 mV and 1012 cm-2 respectively, with low leakage current density. On the contrary, degradation was observed for un-nitrided Al2O3/Ge capacitors after 300 and 400°C post-metal anneals. HfO2/GeON/Ge capacitors benefitted from a 400°C densification anneal but exhibited degradation after post-metal anneals at temperatures greater than 300°C. This degradation is attributed to the influence of Al electrodes on the HfO2 gate stack. HfO2 is considered to be a suitable material for the gate stack and Al2O3 for the buried dielectric in a GeOI structure.

This paper explores the potential of germanium on sapphire (GeOS) wafers as a universal substrate for System on a Chip (SOC), mm wave integrated circuits (MMICs) and optical imagers. Ge has a lattice constant close to that of GaAs enabling epitaxial growth. Ge , GaAs and sapphire have relatively close temperature coefficients of expansion (TCE), enabling them to be combined without stress problems. Sapphire is transparent over the range 0.17 to 5.5 μm and has a very low loss tangent (α) for frequencies up to 72 GHz. Ge bonding to sapphire substrates has been investigated with regard to micro-voids and electrical quality of the Ge back interface. The advantages of a sapphire substrate for integrated inductors, coplanar waveguides and crosstalk suppression are also highlighted. MOS transistors have been fabricated on GeOS substrates, produced by the Smart-cut process, to illustrate the compatibility of the substrate with device processing.

This paper describes the creation of a germanium on sapphire platform, via wafer bonding technology, for system-on-a-chip applications. Similar thermal coefficients of expansion between germanium (5.8×10−6K−1) and sapphire (5×10−6K−1) make the bonding of germanium to sapphire a reality. Germanium directly bonded to sapphire results in microvoid generation during post bond annealing. Inclusion of an interface layer such as silicon dioxide layer by plasma enhanced chemical vapour deposition, prior to bonding, results in a microvoid free bond interface after annealing. Grinding and polishing of the subsequent germanium layer has been achieved leaving a thick germanium on sapphire (GeOS) substrate. Submicron GeOS layers have also been achieved with hydrogen/helium co-implantation and layer transfer. Circular geometry transistors exhibiting a field effect mobility of 890cm2/Vs have been fabricated onto the thick germanium on sapphire layer.

Germanium on sapphire (GeOS) is proposed for system on a chip applications. Sapphire substrates are demonstrated to exhibit lower rf losses and superior crosstalk suppression compared with oxidised silicon handle wafers. Inductors on sapphire also show higher quality factor and better frequency response than those manufactured on an SOI platform. GeOS substrates have been manufactured by wafer bonding. Bond strengths of greater than 2900 mJ m(-2) have been obtained. Thin GeOS has been achieved by He/H-2 ion cut processes. A self-aligned W gate process on Ge has been established with processing temperature limited to 400 degrees C. P channel MOSTs exhibit low threshold voltage and a carrier mobility of about 400 cm(2) V-1 s(-1). (C) 2008 Elsevier Ltd. All rights reserved.

It has been shown that CVD iron from a FC(CO)5 precursor deposits selectively on dielectric surfaces over tungsten surfaces. No similar selective CVD mechanism for titanium and aluminium to SiO2 surfaces was observed. It was established that the selectivity between the tungsten surface and the SiO2 surface could be enhanced through the oxidation of the tungsten surface. Depositions carried out on oxidised tungsten (WOX) and SiO2 substrates showed that iron layers up to 0.5 gm thick with a resistivity of 18 mu Omega cm can be deposited with excellent selectivity. The selective mechanism is attributed to the electrochemical properties of the tungsten or WOX layer, which prevents the reduction of the iron precursor. Selectivity loss was attributed to defects or impurities adsorbed to the tungsten surface. (c) 2007 Elsevier B.V. All rights reserved.

The preferential deposition of CVD iron on silicon dioxide (SiO2) surfaces over tungsten (W) surfaces has been demonstrated. Depositions carried out on patterned W/SiO2 substrates have shown that layers up to a thickness of 180nm with a resistivity value of 19μΩcm can be successfully deposited, exhibiting 100% selectivity; i.e. 180nm of iron was deposited on the oxide surface whilst no deposition occurs on the tungsten surface. For longer deposition times, some iron nucleation was observed on the tungsten surface. It was found that the thickness of the deposited iron layer was inversely proportional to the exposed silicon dioxide surface area.