This work investigated single-event burnout (SEB) and single-event leakage current from drain to source in SiC MOSFETs under femtosecond laser irradiation based on two-photon absorption (TPA), with the aim of investigating how laser-induced carrier generation and distribution affect SEE responses. The devices were irradiated from the front side under controlled laser irradiation conditions, including different laser pulse energies and relative displacements (RD) of the focal plane, to vary the amount and spatial location of laser-induced carriers. No irradiation-relevant gate damage was observed, indicating that the TPA laser irradiation induced specific SEE responses without introducing observable gate degradation. Results showed that the SEB threshold voltage depended on laser-induced carrier generation conditions and device voltage ratings (1.2 kV, 1.7 kV, and 3.3 kV). The SEB threshold voltage of 1.2 kV SiC MOSFETs exhibited a non-monotonic dependence on RD , with the highest sensitivity observed at RD = 3 μm, decreasing from 550 V (RD = 0 μm) to 450 V (RD = 3 μm) and then increasing to 1050 V (RD = 6 μm). These behaviors were interpreted in terms of the effective carrier population within the depletion region, which was influenced by the amount and spatial distribution of laser-generated carriers under different laser energies and focal-plane positions. The observed trends were consistent with reported single-event behavior under low-LET heavy-ion irradiation, highlighting the role of carrier density in understanding the relationship between laser-induced and low-LET heavy-ion-induced SEE responses.

Single-event effects (SEE) in asymmetric trench-gate (ATG) SiC MOSFETs are investigated under both off-state drain bias and on-state gate bias conditions, using pulse-laser two photon absorption (TPA) technique. Conventional SEE evaluations primarily focus on off-state drain bias, whereas the impact of gate voltage during on-state remains insufficiently addressed. In this work, experimental results demonstrate that radiation response and failure characteristics are strongly bias dependent. Off-state irradiation with high drain voltage induces permanent leakage paths associated with combined gate–source and gate–drain oxide degradation. In contrast, on-state irradiation under on-state gate bias mainly results in gate–source oxide damage and exhibits a pronounced threshold laser energy behavior. Post-radiation electrical characterization confirms that all observed failures belong to the single-event leakage current types I (SELC-I) category, with no evident PN junction degradation. Leakage analysis shows that both blocking leakage and gate-bias leakage are governed by trap-assisted tunneling (TAT), while Fowler–Nordheim (FN) and Poole–Frenkel (PF) mechanisms are excluded. A moderate increase in leakage current under high temperature, is consistent with the multi-phonon-enhanced TAT process. These results highlight the necessity of incorporating gate-bias conditions into SEE assessments and provide a more realistic framework for evaluating radiation tolerance and operating margins of SiC power MOSFETs in radiation environments.

This article presents the successful development of high-performance 10-kV-rated, 175-m Omega 4H-SiC MOSFETs with a JFET design width of 0.8-1.2 mu m, an active area of 0.67 cm(2), and a chip size of 1 cm(2). Featuring a three-zone junction termination extension (3-JTE) structure with a total length of 350 mu m, the device demonstrates a superior blocking performance exceeding 12 kV. A key challenge in high-voltage SiC MOSFET design is balancing the reduction of JFET width (W-JFET)-critical for lowering the gate oxide electric field and improving long-term reliability-against the adverse effects of Al ion implantation straggle, which increases JFET resistance. To address this, we optimized the p-well and JFET implantation processes, employing both simulation and experimental validation. The fabricated device achieves the highest rated current and the smallest W-JFET reported to date among 1-kV-rated SiC MOSFETs. Additionally, this article discusses the characteristics of the 10-kV-rated device and offers a comparative analysis of device performance under various fabrication processes. Detailed implementation schemes and final device performance are presented, paving the way for the commercialization of large-area, ultrahigh-voltage (UHV) SiC MOSFETs and enhancing the feasibility of large-scale production for next-generation power electronics applications.

We propose a compact and broadband polarization splitter-rotator (PSR) based on thin-film lithium niobate (TFLN), consisting of two adiabatic tapers and an adiabatic coupler. The TM0 mode is converted into the TE1 mode via the adiabatic taper and subsequently demultiplexed by the adiabatic coupler, thereby achieving polarization splitting and rotation. The fast quasiadiabatic approach is utilized to optimize the geometry of both the taper and the coupler, providing shortcuts to adiabaticity (STA). The length of the taper and the coupler can be reduced to 93 mu m and 94 mu m, respectively. The proposed PSR exhibits an ultra-low excess loss (EL) of less than 0.014 dB for the TE0 mode, and an EL of less than 0.83 dB for the TM0 mode, within the wavelength range of 1400 to 1700 nm. The polarization extinction ratio (PER) for the TE0 mode is greater than 37 dB across the same wavelength range, whereas for the TM0 mode, the bandwidth in which the PER exceeds 20 dB spans 124 nm (from 1494 to 1618 nm). Our research provides a valuable reference for realizing compact adiabatic devices on TFLN, and the proposed PSR could find application in high-density polarization diversity systems. (c) 2025 Society of Photo-Optical Instrumentation Engineers (SPIE)

This paper presents a comprehensive investigation of the short-circuit (SC) failure mechanism and design optimization in an asymmetric trench Silicon Carbide (SiC) power MOSFET. Through a precisely calibrated TCAD simulation framework, we establish correlation with experimental data, accurately replicating both static characteristics and transient SC waveforms. Our spatiotemporal electro-thermal analysis reveals that catastrophic failure is ultimately triggered by the activation of the parasitic bipolar transistor, a process driven by localized self-heating and hole accumulation in the P-body. Furthermore, a systematic parametric study identifies the P body thickness and P+ depth as the most critical structural parameters governing the SC withstand time (SCWT). The analysis quantifies the key trade-off between SC ruggedness and specific on-resistance, providing clear design strategies for enhancing the short-circuit capability of next-generation asymmetric trench power devices.

Heavy-ion induced latent gate damage (LGD) and single-event leakage current (SELC) related to gate damage in silicon carbide (SiC) power MOSFETs were investigated by experiment and simulation. This study verified the strong influence of width and doping concentration of the JFET region of a SiC MOSFET on the sensitivity to heavy-ion-induced gate damage, including LGD and SELC related to gate damage. Failure analysis was conducted to confirm the damage in the gate oxide. Heavy-ion transient technology computer aided design (TCAD) simulations were carried out to confirm the impact of maximum gate oxide electric field during irradiation on gate damage and type of single-event effects (SEEs). This study also provides a feasible way to harden SiC MOSFETs in a radiation environment by reducing the maximum gate oxide electrical field during exposure to heavy ions.

In this paper, the different structures of SiC GTO are designed and compared by Sentaurus Technology Computer Aided Design (TCAD) simulation. The thickness and doping concentration of the epitaxial layers were analyzed and optimized to obtain improved performance trade-off. The cell structure of the active area is studied to achieve a low voltage drop. The implantation-free junction termination extension (JTE) technology is demonstrated, showing a great area efficiency and good process tolerance. In conclusion, an optimized design of SiC GTO structure with high blocking voltage($\gt 15 \mathrm{kV}$) and low conduction voltage drop($\lt 3.6 \mathrm{~V}$) is proposed in this paper. The results indicate that high-performance SiC GTOs can be obtained and the broader application in UHV power device fabrication is expected.

This paper reports the successful demonstration of 10 kV-rated 4H-SiC MOSFETs in a volume-production 6-inch dedicated SiC fab. The device, fabricated with a 10 mm x 10 mm chip size, achieves a low on-resistance of 175 m Omega, and a breakdown voltage of 13 kV by adopting a three-zone Junction Termination Extension (3-JTEs) design. The specific onresistance of the device is 117 m Omega center dot cm(2), which is very close to the theoretical limit for SiC. To reduce the gate oxide electric field, a narrow JFET width (W-JFET) is chosen. However, the low epitaxial doping concentration in 10 kV devices exacerbates the straggling effects of Al ion implantation, causing increased JFET resistance. By using MeV-level HIT ion implantation in the 10 kV-rated SiC MOSFETs, an improved trade-off between JFET width and on-resistance is achieved. Detailed implementation schemes and final device performance are presented, offering a viable path toward the commercialization of large-area, ultrahigh-voltage SiC MOSFETs.

This work presents the design and TCAD simulation of the 19 kV N-channel SiC IGBT based on a P-type substrate. Key device elements-drift layer, N-type fieldstop buffer layer, stepped-doping injection-assist layer, and active cell structure-are systematically optimized to achieve robust blocking performance while minimizing forward voltage drop. On the basis of a $\mathbf{1 1 0} \boldsymbol{-} \boldsymbol{\mu} \mathbf{m}$ drift layer with a doping concentration of $2 \times 10^{14} \mathrm{~cm}^{-3}$, an N-type field-stop (FS) buffer layer was introduced, enabling a simulated breakdown voltage of 19 kV. Moreover, a bilayer buffer stack, which incorporating a low-doped minority carrier injection enhancement (MCIE) layer ($\sim \mathbf{1 0}^{\mathbf{1 5}} \mathbf{~ c m}^{-\mathbf{3}}$), increases conduction current density by $\mathbf{4. 5}$ times and yields a forward voltage drop of 4 V at 100 $A / \mathrm{cm}^{2}$. In the cell structure, high-energy ion implantation was employed to optimize the current spreading layer (CSL), alleviating P-type straggling effect in the low-doped drift region and thereby enlarging the JFET width, reducing its depth, and enhancing device conduction performance. The presented design provides a practical solution for the development of high-voltage SiC bipolar devices with high-current capability.

The ability to generate high fidelity TE-polarized light is significant for the polarization controller (PC). It reflects the performance of PC in orthogonal mode suppression, determining the signal-to-noise ratio and stability of the whole integrated optical system. However, most studies focus on PCs with low insertion loss and compact footprint, few regards polarization extinction ratio (PER) issues. In this paper, we proposed a novel PC based on thin-film lithium niobate (TFLN). Through theoretical analysis of the PER limitations, we performed targeted optimizations on both the splitting ratio control unit and the polarization dependent mode converter (PDMC), reducing the unwanted residual TM0 mode in the circuit greatly. According to the simulations, at the wavelength of 1550 nm, the PER of the proposed TFLN PC can up to > 60 dB, and >similar to 50 dB within tolerance of 24 nm.

This work demonstrates vertical beta-Ga2O3 Schottky Barrier Diodes (SBDs) with a field plate assisted deep mesa termination. The 9 mu m deep mesa is etched using a self-aligned technique to mitigate electric field crowding at the anode edge. Additionally, a dielectric combination of 100nm Al2O3 and 4.8 mu m SiO2 is deposited to fill the trench, enabling the utilization of a field plate to further reduce the electric field at the anode edge. TCAD simulations demonstrate a substantial reduction in the electric field at the anode edge. Owing to the effective termination, the fabricated SBD shows a high breakdown voltage of 2.5kV, which is 2.3 times larger than the unterminated SBDs. The specific on resistance is 3.78m Omega center dot cm(2). Consequently, a high Power Figure of Merit (PFOM) of 1.65GW/cm(2) is hence achieved, which is among the highest in multi-kilovolts Ga2O3 SBDs. Moreover, a remarkably low forward voltage of 1.45V at 100A/cm(2) is also achieved, which is among the lowest in multi-kilovolts Ga2O3 SBDs. The results demonstrate the promising potential of Ga2O3 SBDs for multi-kilovolts applications.

Junction Barrier Schottky (JBS) Diodes are fabricated for the first time on p-type Silicon Carbide (SiC) substrates with the avalanche breakdown voltage (BV) of 1200 V. The SiC p(+) substrates are grown by the top seeded solution growth (TSSG) method, with the average resistivity of 50 m Omega center dot cm and the hole carrier concentration above 1 x 10(20) cm(-3). The conductivity modulation is investigated based on the p-type SiC epitaxy, exhibiting enhanced current capability at elevated temperatures. This study demonstrates the application of p-type SiC substrates in power devices through kilovolt JBS diodes and paves the way towards ultra-high-voltage/current applications of bipolar SiC transistors. Remarkably, we observe an obvious electroluminescence (EL) of the p-type SiC JBS diodes. The luminescence intensity under the carrier recombination mechanism between the conduction band and the Al acceptor energy level has an obvious linear relationship with the conduction current. This finding serves as compelling evidence of the potential of p-type SiC materials in a wide range of applications.

In this work, the vertical GaN trench MIS barrier Schottky (TMBS) rectifier was developed to reduce the leakage current density of the Schottky barrier diode. The vertical GaN TMBS rectifier was fabricated with self-aligned insulator opening process, in order to eliminate the gap between trench and Schottky edge (L-TS). The L-TS is induced by the mask-aligned insulator opening process, which would result in the peak electric field at the edge of Schottky contact on the mesa, leading to increased reverse leakage current. This work studies the influence of the TMBS structure on the device's performance. As mesa width narrows, the reverse leakage current density decreases and the breakdown voltage increases, due to the suppressed electric field at the Schottky interface and at the corner of the trench bottom. The vertical GaN TMBS rectifier exhibits the breakdown voltage of similar to 810 V and the leakage current density of similar to 10(-6) A/cm(2). Furthermore, the forward conduction performance can be improved with hexagonal cell in contrast to the stripe cell, showing the moderate forward voltage drop of similar to 1 V. Besides, the high-temperature performances (up to 200 degrees C) are also presented. These results show that the vertical GaN TMBS diode have great potential for the high-power-density and high-efficiency power electronic applications.

The Floating Island (FI) technology is a promising approach to break the 1D theoretical limit of the power semiconductor devices. However, the Floating Island is confronted with severe turn-on recovery problem due to residue charges in oppositely doped regions after blocking state. In this paper, a novel N+ Buffer is conceived as a solution to the turn-on recovery problem. The SiC Floating Island Schottky Barrier Diode with N+ Buffer (NB-FISBD) is experimentally fabricated and tested. It shows high static performance and effectively suppressed turn-on recovery problem. The NB-FISBD is expected to help the Floating Island devices unleash their potential in power electronic systems.

This work demonstrates a vertical NiO/beta-Ga2O3 Heterojunction Diode (HJD) with a deep trench termination. The 7 mu m deep trench is etched using a self-aligned technique to reduce electric field at the anode edge. Additionally, a combined SiO2/PI/SiO2 dielectric structure is used to fill the trench and an additional field plate is also used to reduce the electric field in Ga2O3. TCAD simulations demonstrate a significant reduction in the electric field at the anode edge. The Mesa-HJD is fabricated along with the DT-HJD. The specific on resistance of them are both 2.4m Omega center dot cm(2). The fabricated DT-HJD shows a high breakdown voltage of >2kV with a doping concentration of 3x10(16)cm(-3). Consequently, a high-Power Figure of Merit (PFOM) of 1.75GW/cm(2) is hence achieved. Moreover, a remarkably low leakage current of 10(-5) A/cm(2) at 1700 reverse bias is also achieved, which is among the lowest in multi-kilovolts Ga2O3 HJDs. The results demonstrate the promising potential of Ga2O3 HJD for power electronics applications.

The impact of the post-trench restoration on the electrical characteristics of vertical GaN power devices is systematically investigated in this work. Following the achievement of microtrench-free GaN trench structure with modified dry etching conditions, the post-trench tetramethylammonium hydroxide (TMAH)-based wet etching and UV/Ozone-based oxidation process are employed to further refine the trench profile. It is shown that the c-plane trench bottom is restored to the level of unetched surface, as evidenced by the improved Schottky interface. Additionally, the post-trench treatment exhibits the anisotropic characteristics with the preferred rounded corner profile on m-plane sidewall compared to a-plane sidewall. The simulations and experimental results demonstrate that the trench MOS barrier Schottky (TMBS) rectifier based on m-plane sidewall could suppress the electric field crowding at the trench corner and, hence, reduce the reverse leakage current by 1–2 orders of magnitude. Furthermore, the MOSCAP test structures were fabricated on the trenches. The extracted interface trap density (Dit) confirms the effective restoration of trench bottom. However, the sidewall surface exhibits the relatively large Dit, which emphasizes the necessity of optimizing the sidewall, particularly for devices incorporating sidewall channel. The demonstrated post-trench restoration technique improves the surface quality and trench structure for the significantly enhanced electrical performances, which is essential for the development of vertical GaN power devices.

Abstract The Floating Island (FI) structure in 4H-SiC device is able to break the “SiC 1D-Limit”. This is achieved by transforming the electric field distribution in the drift region from a single-triangle profile into a multiple-triangle profile, both of which have the same triangle height and width. With such an electric field distribution, the trade-off between breakdown voltage (BV) and specific ON-resistance (RON,sp) can be significantly improved. In this paper, the 4H-SiC FI Junction Barrier Schottky (JBS) diodes with four different island layouts, namely the stripe, the hexagon island, the hexagon hole and the hexagon cell, have been fabricated and tested. The results show that RON,sp is virtually the same at the same N-type area ratio, but BV diverges at the same N-type area ratio for different layouts. The stripe layout has the highest BV among the four island layouts. A BV of 2200V and RON,sp of 3.8mΩ.cm2 has been achieved with the stripe design.

In this paper, the 4H-SiC super-junction (SJ) Schottky barrier diode (SBD) with hexagonal cell has been fabricated by trench etching and epitaxial regrowth process. The fabricated device achieves a breakdown voltage (BV) of 3570V with specific on-resistance (R-on,R-sp) of 4.5m Omega.cm(2) which breaks the one-dimensional performance limit of the SiC unipolar device. The impact of SJ's mesa width on static I-V and C-V characteristic has also been investigated. With a double pulse test, the fabricated device performs high speed switching over 50kV/mu s. The repetitive surge current test is also carried out on the fabricated device to demonstrate its surge robustness.

This Letter demonstrates a high-performance 3.3 kV-class β-Ga2O3 vertical heterojunction diode (HJD) along with an investigation into its off-state leakage mechanism. The vertical β-Ga2O3 HJD with field plate assisted deep mesa (FPDM) termination was fabricated using a self-aligned technique to etch the deep mesa to a depth of 9 μm, thereby reducing electric field crowding at the anode edge. In addition, a thick dielectric is deposited to fill the trench, facilitating the utilization of a field plate to further reduce the electric field at the anode edge. TCAD (Technology Computer Aided Design) simulations show significant suppression of electric field crowding at the anode edge. The fabricated HJD exhibits a high current swing of ∼1010 over a temperature range from 25 °C to 175 °C. The specific on-resistance (Ron,sp) is extracted to be 3.9 mΩ cm2, and the breakdown voltage is 3.42 kV with the FPDM termination. These conduction and blocking characteristics lead to a high power figure of merit of 3 GW/cm2, which is one of the highest among multi-kilovolt β-Ga2O3 diodes. Furthermore, the off-state current leakage mechanism of the HJD under a reverse bias up to 2000 V was investigated. The fitted results reveal that the leakage current is primarily dominated by Poole–Frenkel (PF) emission, with the trap level of PF extracted to be 0.36 eV below the conduction band of NiO.

The threshold voltage $(V_{TH})$ of silicon carbide (SiC) MOSFETs are affected by the coupled effect including the SiO 2 /SiC poor interface and the short channel effects (SCEs), and this coupled effect is directly related to gate voltage $(V_{GS})$ and drain voltage $(V_{DS})$ . This paper introduces a discrete channel model to estimate the V TH deviation caused by the different voltage stress on both sides of SiC MOSFET short channel. Transfer characteristics are used to verify the accuracy of the model. It is indicated that the poor interface is the dominant factor for these deviations of $V_{TH}$ , Power MOSFETs were fabricated to further validate the model and revealed that the source resistance also contributes to the deviations especially with the increasing of drain-source current in MOSFET.