Floating Island (FI) structure can efficiently modulate electric field distribution and improve device performance beyond one-dimensional limit, but it faces severe switching problem which hinders its application. In this work, a SiC FI Junction Barrier Schottky (JBS) diode with novel N+ Buffer (NB) in the 2-layer FI is fabricated to address the dynamic challenge. The fabricated SiC NB-FI JBS diode shows a high static performance with a breakdown voltage (BV) of 4kV and a specific on-resistance (Ron,sp) of 5.7 mΩ·cm². By FI multi-parameter co-design, the 2-layer NB-FI JBS diode demonstrates fast turn-on capability in both quasi-dynamic tests and switching tests without evident turn-on voltage overshoot, which is in clear contrast to the conventional FI JBS diode. Therefore, the effectiveness of NB is successfully validated. Furthermore, reverse recovery characteristics of the NB-FI JBS diode are also studied/investigated, exhibiting a fast unipolar turn-off process. Above results confirm the fast switching capability of the high performance SiC NB-FI device, indicating the bright future of the NB-FI concept for the next generation high performance power devices.

Ultra-wide bandgap(UWBG)semiconductors,including gallium oxide(Ga2O3),aluminum nitride(AlN),boron nitride(BN),and diamond,have garnered significant attention due to their substan-tial critical electric fields(E-field).Among these,β-Ga2O3 stands out due to its exceptional properties,such as a broad spectrum of controllable N-doping,a decent electron mobility,and the read-ily available large-scale melt-grown substrates.These advantages promote high-quality homoepitaxy and potentially cost-effective device fabrication[1].Edge termination is pivotal for vertical β-Ga2O3 power devices.However,the lack of effective native p-type doping poses challenges in managing the electric field in β-Ga2O3.To address this issue,various innovative techniques have been de-veloped[2].

This study presents a vertical beta-gallium oxide (beta-Ga2O3) hetero-junction diode (HJD) featuring a self-aligned multi-zone junction termination extension (SA-MZJTE), achieving a breakdown voltage of 3.9 kV. The SA-MZJTE requires only an additional self-aligned etching process following the deposition of 3 -layer NiO single -zone JTE device. The 3-layer NiO configuration is designed to co-optimize the charge and breakdown field distribution (NiO breakdown field is closely related to its doping level), in order to exploit the blocking potential of NiObased JTE. The fabricated SA-MZJTE HJD demonstrates a breakdown voltage of 3.9 kV with a long JTE length of 20 mu m. The specific on-resistance is extracted to be 3.5 m Omega center dot cm(2), resulting in a power figure of merit (PFOM) of 4.3 GW/cm(2). Furthermore, the SA-MZJTE HJD also maintains excellent blocking capability at elevated temperature, demonstrating a breakdown voltage over 3,000 V at 175 degrees C. This excllent high -temperature blocking capability enables its operation at harsh conditions. A medium area device is also fabricated which demonstrates repetitive 2600 V blocking capability. The performance of the SA-MZJTE HJD is among the highest in reported multi-kilovolt Ga2O3 diodes. These results exhibit that the SA-MZjTE is an effective and promising termination solution for medium- and high-voltage, high-temperature Ga2O3 power applications.

In this paper, 3.3kV-class 4H-SiC Super-junction (5 J) PiN diodes are fabricated by trench etching and epitaxial regrowth process. The mechanism of incomplete ionization is analyzed through layout-dependent I-V and temperaturedependent C -V measurements. A double-pulse test is carried out to study the reverse recovery behavior of the device. Surge current capability has also been evaluated, demonstrating a maximum surge current density of 4000 A/cm'. Furthermore, the evolution of conductance modulation and failure mechanisms under increasing surge current conditions is analyzed. The influence of device layout on surge current characteristics is explored, illustrating the impact of P-pillar area variation and incomplete ionization. The device reliability is evaluated through repetitive surge current test. A 25% increase in specific on-resistance has been observed after 4000 cycles of 3000 A/cm" surge current. These studies provide experimental evaluations for the electrical behavior and reliability of the 4H-SiC SJ-PiN diodes, contributing to the advancement of SiC power device technology.

In this work, we propose a p-NiO/n-Ga2O3 hetero-junction (HJ) Schottky barrier diode (SBD) with low turn-on voltage (V-on) and high breakdown voltage (BV) with a trench SBD as a control. An investigation of its electrical characteristics is simulated by Sentaurus TCAD. The HJ SBD utilizes a low work-function anode metal to form a top electrode by reducing the V-on of the diode at the forward state. A fin structure and metal/semiconductor (M/S) junction or PN HJ was employed to achieve an enhanced BV at the reverse state. An attempt to optimize the electrical characteristics of the device by modifying its structural parameters is also comprehensively analyzed in this work. The HJ SBD achieves a low V-on of 0.57 V and a Power Figure of Merit (P-FOM) of 3.79 GW/cm(2), simultaneously. The proposed structure provides a new approach for realizing high performance beta -Ga2O3 SBDs with high reverse blocking and low loss capabilities.

Deep mesa is an effective edge termination widely deployed in high-voltage power devices. However, its effectiveness requires the minimal distance between mesa and electrode edge and is susceptible to charges in the dielectric passivation, posing challenges in practical implementation. Here, we propose a deep mesa termination encapsulated by p-type materials, which functions as a reduced-surface-field (RESURF) structure and enables a wide design and process window. We demonstrate the RESURF-mesa design in vertical Ga3O3 diodes. In this design, a 5 μm deep mesa, which is intentionally not aligned with the anode edge, is encapsulated by p-type nickel oxide (NiO). This termination has been applied to devices on three Ga2O3 wafers with epitaxial doping concentrations ranging from 1.2 × 1016 to 5 × 1016 cm−3, enabling an average one-dimensional junction field of 4.2–4.4 MV/cm in all wafers. Additionally, the diode with 1.2 × 1016 cm−3 doping achieves a specific on-resistance (RON,sp) of 4.05 mΩ·cm2 and a breakdown voltage of 3214 V, resulting in a power figure of merit of 2.55 GW/cm2, which is among the highest in multi-kilovolt β-Ga2O3 diodes. The above results demonstrate the RESURF-mesa termination as a versatile and effective solution for wide bandgap and ultra-wide bandgap power devices.

In this paper, 3kV full-SJ and semi-SJ Schottky Barrier Diodes (SBDs) were fabricated with charge-imbalance super junction termination (CI-SJTE) using trench-filling regrowth method. It was experimentally demonstrated that the CI-SJTE achieves a breakdown voltage (BV) of 3399V (85% of the simulated ideal parallel plane BV) for the semi-SJ and 3099V (77%) for the full-SJ, respectively. Furthermore, the termination simulations show that when the P charge is overcompensated, the high electric field crowding in the semi-SJ is lower than that in the full-SJ, since the high electric field in the semi-SJ is confined to the N- buffer rather than the ise substrate. Therefore, the semi-SJ are able to achieve 3600V (90%) with CI-SJTE, which is obviously higher than the 3211V (80%) of the full-SJ in simulations. This work shows that it is possible for the 4H-SiC semi-SJ devices to achieve high terminal efficiency without additional surface termination structure.

In this work, an analytical model is developed to characterize the electric field distribution and avalanche breakdown mechanism in $\text{4 H}$-SiC tilted super-junction (SJ) devices. The impact of tilt angle on the electric field distribution has been modeled and validated through numerical simulations. It is found that the critical avalanche breakdown path shifts with tilt angles. For $\text{4 H}$-SiC SJ devices with a tilt angle of $\text{8 8}^{\boldsymbol{\circ}}$, the breakdown voltage (BV) initially increases with aspect ratio, followed by a sharp decline beyond an aspect ratio of 8. In contrast, non-tilted SJ devices exhibit a continuous increase in BV, even at aspect ratios up to 25. Moreover, a tilt angle less than 90° broadens the charge imbalance tolerance window for a given BV, thereby enhancing manufacturability. By combining the avalanche breakdown model with specific on-resistance model, the figure of merit (FOM) for $\text{4 H}$-SiC tilted SJ devices is derived. The optimal tilt angle for maximizing FOM is found to depend on the BV rating when the SJ pillar width is fixed. The proposed model and findings offer valuable insights and serve as a design guideline for optimizing $\text{4 H}$-SiC SJ devices by incorporating tilt angle as a novel design parameter.

This work demonstrates high-performance vertical beta-Ga2O3 rectifiers featuring a reduced-surface-field mesa (RESURF-mesa) structure. This RESURF-mesa design employs nonself-aligned etching to form a 5-mu m deep mesa, utilizing a 5-mu m-thick SiO2 layer and 120-nm p-type nickel oxide (NiO) to encapsulate the sidewalls with an argon-to-oxygen flux ratio of 20:1. Technology computer-aided design (TCAD) simulations confirm a reduced surface electric field (E-field) with an optimized NiO thickness. Consequently, the RESURF-mesa Schottky barrier diode (SBD) with 120-nm NiO exhibits a breakdown voltage (BV) of 2600 V, while the RESURF-mesa heterojunction diode (HJD) sustains a reverse voltage exceeding 3000 V due to the stronger heterointerface. The specific ON-resistance (R-ON,R-sp) of both devices is 4.1 m Omega & sdot;cm(2), yielding the power figure of merit (PFOM) of 1.6 GW/cm(2)for RESURF-mesa SBD and 2.2 GW/cm(2 )for RESURF-mesa HJD. The performance of both rectifiers is among the highest in reported multikilovolts Ga2O3 SBDs and HJDs. Additionally, we have investigated the origin of sidewall leakage current and developed methods to suppress it, which is also effective at high temperatures. These findings underscore the significant potential of RESURF-mesa technology in advancing multikilovolt Ga2O3 device applications.

This paper reports the successful demonstration of 10 kV-rated 4H-SiC MOSFETs in a volume-production 6-inch dedicated SiC fab. The device, fabricated with a 10 mm x 10 mm chip size, achieves a low on-resistance of 175 m Omega, and a breakdown voltage of 13 kV by adopting a three-zone Junction Termination Extension (3-JTEs) design. The specific onresistance of the device is 117 m Omega center dot cm(2), which is very close to the theoretical limit for SiC. To reduce the gate oxide electric field, a narrow JFET width (W-JFET) is chosen. However, the low epitaxial doping concentration in 10 kV devices exacerbates the straggling effects of Al ion implantation, causing increased JFET resistance. By using MeV-level HIT ion implantation in the 10 kV-rated SiC MOSFETs, an improved trade-off between JFET width and on-resistance is achieved. Detailed implementation schemes and final device performance are presented, offering a viable path toward the commercialization of large-area, ultrahigh-voltage SiC MOSFETs.

The 4H-SiC Floating Island (FI) device can break the 1-D SiC limit due to its ability to modulate the electric field in the drift region. In the previous research, we utilized the N+ buffer to overcome the forward recovery issue of the FI device. However, the FI device with N+ buffer can still suffer from repetitive forward recovery. In this work, we take the Floating Island JBS (FIJBS) as the research object. We will elucidate the cause of the repetitive recovery issue in the Fl device and analyze the dynamic equilibrium mechanism of electron-hole pairs. We also simulate the impact of the floating island width on the device's static and dynamic characteristics, which is beneficial for selecting an appropriate island width. To further improve the repetitive recovery performance of the device, we propose a novel structure with width-optimized islands. Simulation results indicate that the recovered resistance of the new structure is significantly reduced even after repetitive switching tests compared with the conventional FJBS. Moreover, this novel structure only changes the island width without requiring complex manufacturing processes. Those results demonstrate the great potential of this new structure for high performance power device.

The short-circuit (SC) robustness of SiC MOSFETs is critical for high-power applications, yet 1.2 kV devices often struggle to meet the industry-standard SC withstand time (SCWT) under practical operating conditions. Despite growing interest in higher voltage classes, no prior study has systematically evaluated the SC performance of 1.7 kV SiC MOSFETs. This study provides the first comprehensive evaluation of commercially available 1.7 kV SiC MOSFETs, analyzing their SC performance under varying electrical stress conditions. Results indicate a clear trade-off between SC withstand time (SCWT) and drain-source voltage (VDS), with SCWT decreasing from 32 µs at 400 V to 4 µs at 1100 V. Under 600 V, a condition representative of practical use cases in many high-voltage applications, the devices achieved an SCWT of 12 µs, exceeding the industry-standard 10 µs benchmark—a threshold often unmet by 1.2 kV devices under similar conditions. Failure analysis revealed gate dielectric breakdown as the dominant failure mode at VDS ≤ 600 V, while thermal runaway was observed at higher voltages (VDS = 800 V and 1100 V). These findings underscore the critical importance of robust gate drive designs and effective thermal management. By surpassing the shortcomings of lower voltage classes, 1.7 kV SiC MOSFETs can be a more reliable, and efficient choice for operating at higher voltages in next-generation power systems.

This work demonstrates vertical beta-Ga2O3 Schottky Barrier Diodes (SBDs) with a field plate assisted deep mesa termination. The 9 mu m deep mesa is etched using a self-aligned technique to mitigate electric field crowding at the anode edge. Additionally, a dielectric combination of 100nm Al2O3 and 4.8 mu m SiO2 is deposited to fill the trench, enabling the utilization of a field plate to further reduce the electric field at the anode edge. TCAD simulations demonstrate a substantial reduction in the electric field at the anode edge. Owing to the effective termination, the fabricated SBD shows a high breakdown voltage of 2.5kV, which is 2.3 times larger than the unterminated SBDs. The specific on resistance is 3.78m Omega center dot cm(2). Consequently, a high Power Figure of Merit (PFOM) of 1.65GW/cm(2) is hence achieved, which is among the highest in multi-kilovolts Ga2O3 SBDs. Moreover, a remarkably low forward voltage of 1.45V at 100A/cm(2) is also achieved, which is among the lowest in multi-kilovolts Ga2O3 SBDs. The results demonstrate the promising potential of Ga2O3 SBDs for multi-kilovolts applications.

Silicon Carbide (SiC) MOSFETs have gained significant attention in power electronics for their superior characteristics. Despite advances in 1.2kV SiC MOSFET generations, a comprehensive comparative analysis of different device types remains limited. This study examines the short-circuit (SC) behavior of 1.2kV SiC MOSFETs across multiple vendors and generations, including planar and trench structures. Key metrics such as Short Circuit Withstand Time (SCWT), SC energy, SC peak power, SC energy density, and SC current density were evaluated at DC bus voltages of 400V, 600V, and 800V. Our findings reveal that third-generation (3G) devices exhibit inferior SC performance due to smaller die areas that impede heat dissipation, with 800V survival times as low as 2.25 mu s for GeneSiC-3G. In contrast, trench-based designs showed improved resilience. Infineon-1G, with an active area 44.3% smaller than Littelfuse-1G and 45% smaller than CREE-2G, achieved comparable SCWT ( 4.5 mu s vs. 4.5 mu s for Littelfuse and 4 mu s for CREE-2G) while demonstrating superior thermal management, with a SC energy density of 0.096 J/mm(2) and current density of 41.74 A/mm(2) at 800V. Similarly, another trench device, Rohm-3G, outperformed planar 3G devices, with a SCWT of 3.5 mu s and peak power of 110 kW at 800V. Post-SC failure mechanisms were systematically analyzed using optical microscopy, Lock-In Thermal Emission Microscopy (LITEM), and Focused Ion Beam (FIB), revealing gate leakage paths and damage in the active regions and two-finger area. These findings offer significant insights into the trade-offs between on-state performance and SC robustness, providing manufacturers and designers with crucial guidance for developing optimized SiC MOSFET designs for high-power applications.

The poor interface of silicon carbide (SiC)/SiO2 combined with the short channel effects (SCEs) and source contact resistance, collectively impacts the effective threshold voltage in SiC MOSFETs. In this work, a physical discrete channel model was proposed to analyze the influence of the combined effects of varying channel lengths, as well as applied drain and gate voltages. The proposed model was validated through TCAD simulation and by the fabricated SiC power MOSFETs. This model was applicable to MOSFETs with both symmetric and asymmetric channels considering various interface state density distributions. The influence of these factors on effective threshold voltage was also discussed considering variations in source contact resistance and channel doping concentration. Through the analysis of the model results, it was found that the interface states significantly impact the effective threshold voltage through different mechanisms while the SCEs are mitigated by the unsaturated interface states.

Junction Barrier Schottky (JBS) Diodes are fabricated for the first time on p-type Silicon Carbide (SiC) substrates with the avalanche breakdown voltage (BV) of 1200 V. The SiC p(+) substrates are grown by the top seeded solution growth (TSSG) method, with the average resistivity of 50 m Omega center dot cm and the hole carrier concentration above 1 x 10(20) cm(-3). The conductivity modulation is investigated based on the p-type SiC epitaxy, exhibiting enhanced current capability at elevated temperatures. This study demonstrates the application of p-type SiC substrates in power devices through kilovolt JBS diodes and paves the way towards ultra-high-voltage/current applications of bipolar SiC transistors. Remarkably, we observe an obvious electroluminescence (EL) of the p-type SiC JBS diodes. The luminescence intensity under the carrier recombination mechanism between the conduction band and the Al acceptor energy level has an obvious linear relationship with the conduction current. This finding serves as compelling evidence of the potential of p-type SiC materials in a wide range of applications.

Abstract Silicon Carbide (SiC) MOSFETs are efficient alternatives for power electronics, yet concerns persist regarding their short-circuit withstand capability compared to traditional Si IGBTs. Despite the market evolution of 1200V SiC MOSFET generations, a comprehensive comparative analysis of different device types is lacking. This study addresses this gap, comparing five planar and one trench device representing 1st (1G), 2nd (2G), and 3rd generation (3G) products. The SCWT, short circuit energy and short circuit peak power values are also compared. Findings show 3G devices exhibit inferior performance, indicating a compromise between on-state losses reduction and short-circuit ruggedness. The cause behind this seems to be that the smaller die area in 3G hinders heat dissipation during faults, thereby reducing short-circuit withstand time. Furthermore, 2G device display higher resilience at 400V, this advantage diminishes at higher voltages (⩾600V). Notably, 800V 3G devices exhibit survival times as low as 2 μs, with failure analysis identifying gate oxide dielectric breakdown at 400V and thermal runaway at voltages ⩾600V across all.

In this work, a novel silicon carbide lateral MOSFET (SiC LMOS) structure with ohmic contact on multiple P-islands is proposed to resolve the dynamic problem in multiple P-islands structure. In the conventional structure, although the introduction of multiple P-islands can increase the breakdown voltage (BV), the dynamic specific on-resistance $(R_{\text{on},\text{sp}})$ is increased to an enormously large value due to the unrecoverable depletion of multiple P-islands after blocking state. This work addresses this issue with the proposed structure and validated with numerical simulation. The static simulation curves indicate the static characteristic including BV and Ron, sp of the proposed device is close to that of the conventional structure. On the other hand, the dynamic simulations including gate charge simulation and double pulse simulation, show that compared with the conventional device, the gate charge FOM $(R_{\text{on},\text{sp}}\times Q_{\text{GD}})$ is largely reduced and the dynamic $R_{\text{on},\text{sp}}$ of the proposed device is significantly reduced by several magnitude from $3.21\times 105\ \mathrm{m}\Omega\cdot \text{cm}^{2}$ to 265.6 m $\Omega\cdot \text{cm}^{2}$ which equals its static $R_{\text{on},\text{sp}}$. In addition, the switching loss is reduced by 70.5%. The mechanism for the improved performance is discussed in detail with carrier transport analysis.

In this work, the vertical GaN trench MIS barrier Schottky (TMBS) rectifier was developed to reduce the leakage current density of the Schottky barrier diode. The vertical GaN TMBS rectifier was fabricated with self-aligned insulator opening process, in order to eliminate the gap between trench and Schottky edge (L-TS). The L-TS is induced by the mask-aligned insulator opening process, which would result in the peak electric field at the edge of Schottky contact on the mesa, leading to increased reverse leakage current. This work studies the influence of the TMBS structure on the device's performance. As mesa width narrows, the reverse leakage current density decreases and the breakdown voltage increases, due to the suppressed electric field at the Schottky interface and at the corner of the trench bottom. The vertical GaN TMBS rectifier exhibits the breakdown voltage of similar to 810 V and the leakage current density of similar to 10(-6) A/cm(2). Furthermore, the forward conduction performance can be improved with hexagonal cell in contrast to the stripe cell, showing the moderate forward voltage drop of similar to 1 V. Besides, the high-temperature performances (up to 200 degrees C) are also presented. These results show that the vertical GaN TMBS diode have great potential for the high-power-density and high-efficiency power electronic applications.

In this letter, 4H-SiC super-junction (SJ) Schottky diodes (SBDs) with hexagonal cell were fabricated by trench etching and epi-regrowth process. Quasi-selective epi-regrowth in hexagonal trenches and high aspect ratio of 6 for P-pillars without voids were achieved. Furthermore, a termination with field limiting ring assisted super-junction termination extension (RA-SJTE) was proposed and adopted to suppress the high electric field around the device edge. With such a termination, the breakdown voltage (BV) significantly increases from 1530 V to 4150 V (92% of the TCAD simulation value). The specific on-resistance (R-ON,R-sp) of the fabricated device is 4.6 m Omega.cm(2), demonstrating a performance higher than the one-dimensional limit of 4H-SiC unipolar devices. These results show the promising future of high-performance 4H-SiC SJ device for multi-kilovolts application.