SAEAES is a lightweight authentication encryption proposed at the cryptographic hardware and embedded systems conference in 2018, which is applicable to resource-constrained scenarios. In this study, under the ciphertext-only assumption, random single-byte faults were adopted, and a novel ciphertext-only fault analysis method named slide differential statistical fault analysis was proposed. The method was derived from slide analysis, and differential relations were combined with statistical fault analysis. Faulty ciphertexts and tags were collected by randomly injecting single-byte faults, and the SAEAES algorithm was decrypted via statistical analysis. A novel Random Forest distinguisher based on machine learning was also designed in this paper. The number of fault injection rounds was increased by one by the proposed sliding differential statistical fault analysis method. A minimum of 78 faults were required by the Random Forest distinguisher to recover the 128-bit original key of SAEAES. Focusing on the novel ciphertext-only analysis, the findings facilitate further research on lightweight cryptographic algorithms.

Intrusion detection systems (IDS) for control area network (CAN) bus communication using deep learning models face threats from adversarial closed-box. attacks in the Internet of Vehicles (IoVs). Although watermark techniques are proposed as defences, they lack concealment and are vulnerable. Current watermark methods for time-series data-based applications need cloud-based verification and terminal-based generation, and they cannot meet real-time requirements with large resources. To address these issues, we propose a real-time gated recurrent units (GRUs) based IDS with for CAN bus communication via a novel dynamic label watermark (DLW) method. In detail, we design a multitask learning structure at the terminal side only to detect conventional intrusion attacks. At the same time, we propose a novel DLW method applied to time-series data to defend against adversarial closed-box. attacks. Experimental results show that for the detection of Denial of Service (DoS), revolutions per minute (RPM) spoofing, and fuzzing attacks, our model achieves 1.00000, 1.00000, and close to 1.00000 with the recall, accuracy, F1 score, and precision, respectively. For detection of gear spoofing, our model with the same metrics achieves 1.00000, which are 0.0882, 0.0001, 0.0459, and 0.0208 better than CANLite and the same as ConvLSTM-GNB. Finally, we construct a new adversarial closed-box. attack embedded with four attacks above to validate the resistance and performance of our model (achieving 116 KB code size), which is 58% smaller, 0.9%-35.7% faster, and 1.52%-10.5% improvement of same metrics compared to the baseline model (LSTM).

A novel ciphertext-only fault analysis method termed algebraic statistical fault analysis was proposed for enhancing the implementation security of the LEA algorithm in light of its structural and implementation characteristics. Based on the random nibble-oriented fault model, algebraic relationships were analyzed and constructed, and coupled with statistical inference between pre-injection and post-injection intermediate states, the LEA algorithm was decrypted. Additionally, Hellinger distance, Hellinger distance-Hamming weight, and Hellinger distance-maximum likelihood distinguishers were designed. Experimental results demonstrate that the proposed method extends fault injection to an additional deeper round, and the novel distinguisher successfully recovers the 128 bit secret key of the LEA algorithm with a minimum of 72 fault injections, providing valuable references for security evaluation of other cryptographic algorithms in smart small devices.

The tutorial explores key security and functional safety challenges for Artificial Intelligence (AI) in embedded automotive systems, including aspects from adversarial attacks, long life cycles of products, and limited energy resources of automotive platforms within safety-critical environments in diverse use cases. It provides a set of recommendations for how the security and safety engineering of machine learning can address these challenges. It also provides an overview of contemporary security and functional safety engineering practices, encompassing up-to-date legislative and technical prerequisites. Finally, we identify the role of AI edge processing in enhancing security and functional safety within embedded automotive systems.

The Controller Area Network (CAN) protocol, as the core communication protocol for vehicular networks, is susceptible to various cyber attacks due to its openness and lack of security measures. Moreover, the severe imbalance between normal and abnormal (attack) data in vehicular communication, with a ratio of $13: 1$, makes detecting attack behaviors extremely challenging. First, to address the data imbalance issue, this paper proposes a data augmentation method using the Adaptive Synthetic Sampling (ADASYN) technique to enhance and balance the dataset. Then, to detect CAN bus intrusions, an improved Bi-LSTM model is proposed, which introduces a self-attention mechanism to capture critical information from CAN messages, enhancing the model’s ability to detect intrusions in CAN messages. Finally, experimental results show that, compared to Recurrent Neural Network (RNN), Long Short-Term Memory (LSTM), ResNet, and EfficientNet, our method achieves an accuracy, precision, and F1 score of $0.9970,0.9880$, and 0.9888, respectively, with a model size of 2.6 MB.

Software-defined vehicles (SDVs) make automotive systems more intelligent and adaptable, and this transformation relies on hybrid automotive in-vehicle networks that refer to multiple protocols using automotive Ethernet (AE) or a controller area network (CAN). Numerous researchers have developed specific intrusion-detection systems (IDSs) based on ResNet18, VGG16, and Inception for AE or CANs, to improve confidentiality and integrity. Although these IDSs can be extended to hybrid automotive in-vehicle networks, these methods often overlook the requirements of real-time processing and minimizing of the false positive rate (FPR), which can lead to safety and reliability issues. Therefore, we introduced an IDS based on the Swin Transformer to bolster hybrid automotive in-vehicle network reliability and security. First, multiple messages from the traffic assembly are transformed into images and compressed via two-dimensional wavelet discrete transform (2D DWT) to minimize parameters. Second, the Swin Transformer is deployed to extract spatial and sequential features to identify anomalous patterns with its attention mechanism. To compare fairly, we re-implemented up-to-date conventional network models, including ResNet18, VGG16, and Inception. The results showed that our method could detect attacks with 99.82% accuracy and 0 FPR, which saved 14.32% in time costs and improved the accuracy by 1.60% compared to VGG16 when processing 512 messages.

Electronic control units (ECU) have been widely used in modern resource-constrained automotive systems, com-municating through the controller area network (CAN) bus. However, they are still facing man-in-the-middle attacks in CAN bus due to the absence of a more effective authenti-cation/encryption mechanism. In this paper, to defend against the attacks more effectively, we propose a unified lightweight authenticated encryption that integrates recent prevalent cryp-tography standardization Isap and Ascon.First, we reuse the common permutation block of ISAP and Asconto support authenticated encryption and encryption/decryption. Second, we provide a flexible and independent switch between authenticated encryption and encryption/decryption to support specific application requirements. Third, we adopt standard CAESAR hardware API as the interface standard to support compatibility between different interfaces or platforms. Experimental results show that our proposed unified lightweight authenticated encryption can reduce 26.09% area consumption on Xilinx Artix-7 FPGA board compared with the state-of-the-arts. In addition, the encryption overhead of the proposed design for transferring one CAN data frame is $\mathbf{10.75} \mu s$ using Asconand $\mathbf{72.25} \mu s$ using ISAP at the frequency of 4 MHz on embedded devices.

Nowadays, hardware-based AES faces more than one type of Side-Channel-Attacks (SCA), such as the Differential Power Analysis (DPA) attack and the Differential Fault Analysis (DFA) attack. However, most of the current DFA-resistant implementations of AES only focus on resisting the DFA attack but with minimal concurrent considerations on their DPA resistance capability. In this paper, we propose a fault resistant AES with DPA awareness. First, we evaluate the DPA resistance for different implementation architectures of AES before the implementation with S-Box over GF(2 4 ) 2 is selected. Second, we evaluate the DPA resistance for different fault detection architectures before the concurrent fault detection method is selected. Third, we propose a novel fault resistant technique for AES using input-output differential tables over GF(2 4 ) 2 . We have performed tests based on Partial Guessing Entropy (PGE) to evaluate the DPA resistance for the existing DFA-resistant designs and our proposed design. Experimental results prove that our design has a slower convergence speed (around 33%) with a 100% fault coverage rate and less area than the existing countermeasure designs for fault injection. Results also show that the fault detection designs weaken their DPA resistance, which indicates the importance of co-design of DFA and DPA to achieve less power information leakage.

Artificial Intelligence (AI) has been widely applied in Anomaly Detection System (ADS) in-vehicle networks. ADS should be able to detect abnormal behaviors and attacks at the gateway Electronic Control Unit(ECU). The detection is usually required with low latency to leave as much as possible time budget to apply proper protections once an anomaly is successfully detected. However, AI models are very vulnerable to the type of Blackbox attacks, which do not require prior knowledge of either the deep learning model internals or the model's training data for a hacker. In this paper, first, we propose a new optimized method to adopt Long Short Term Memory (LSTM) deep learning model for the ADS in-vehicle network, which leads to an efficient detection system. The optimization has been done based on the characteristics of the dataset from practical CAN in-vehicle network together with tuning existing parameters of the LSTM model. Second, we propose an efficient Blackbox attack to the adopted ADS using the LSTM model, which only requires a small test dataset to train a new victim model (input/output is compatible with the original model). Experimental results show that we only require around 50 man-hours to build a victim model that leads to the wrong interpretation compared to the original model without the Blackbox attack. It proves that the whole community should not only focus on developing efficient ADS, but also on how to protect it in future work.

With the emergence of smart automotive devices, the data communication between these devices gains increasing importance. SOME/IP is a light-weight protocol to facilitate interprocess/device communication, which supports both procedural calls and event notifications. Because of its simplicity and capability, SOME/IP is getting adopted by more and more automotive devices. Subsequently, the security of SOME/IP applications becomes crucial. However, previous security testing techniques cannot fit the scenario of vulnerability detection SOME/IP applications due to miscellaneous challenges such as the difficulty of server-side testing programs in parallel, etc. By addressing these challenges, we propose Ori - a greybox fuzzer for SOME/IP applications, which features two key innovations: the attach fuzzing mode and structural mutation. The attach fuzzing mode enables Ori to test server programs efficiently, and the structural mutation allows Ori to generate valid SOME/IP packets to reach deep paths of the target program effectively. Our evaluation shows that Ori can detect vulnerabilities in SOME/IP applications effectively and efficiently.

密码设备在进行加解密时会产生大量的物理信息,如电磁、能耗、热量等.攻击者利用这些物理信息对密码设备进行侧信道攻击,窃取密码设备的密钥.就传统的椭圆曲线加密算法简单能量分析攻击而言,攻击者通过人工识别倍点计算能耗数据中的相似模块,从而恢复出密钥.这种攻击方式导致攻击效率低,准确率不高.本文基于时间序列的模体发现提出了SPAMD算法,该算法实现了倍点计算的能耗数据中相似模块的自动识别,完成了攻击方式从人工识别到自动识别的转换.实验结果表明SPAMD攻击在效率和准确率上有了显著的提升.

在电子数据取证领域,取证与反取证技术的较量不断升级.数据加密技术是反取证技术的一个重要研究分支.为了在这场较量中占有先机,文中重点研究了物联网领域中所采用的LED轻量级密码算法,通过分析LED算法的加、解密过程,引入积分故障分析对其进行安全性分析,提出了一种破解LED密码算法的积分故障分析方法.积分故障分析主要利用同一明文正常加密输出的密文与注入故障后产生的密文之间的差异,通过在加密过程中注入随机故障获得故障密文;并通过一个积分故障识别器,恢复最后一轮的子密钥值,进而获得最后一轮的加密输入,它是倒数第二轮的输出.重复上述过程,直到加密密钥可以通过密钥生成算法获得.在上述推导的基础上进行实验仿真测试,从精确度、可靠性和时间复杂度3个方面证明了积分故障分析方法可以在有效时间内通过构造一个基于半字节故障模型的3轮故障识别器来实现破解过程.该方法可以为破解AES类轻量级加密算法提供参考与借鉴.

We propose a Profiling through Relevance-Learning (PRL) technique on Physical Leakage Information (PLI) to extract highly correlated PLI with processed data, as to achieve a highly efficient yet robust Side Channel Attack (SCA). There are four key features in our proposed PRL. First, variance analysis on PLI is implemented to determine the boundary of the clusters and objects of the clusters. Second, the nearest-neighbor k-NN variance clustering is used to reduce the sampling points of PLI by clustering the high variance sampling points and discarding the low variance sampling points of PLI measurements (traces). These clustered sampling points, which are highly correlated with the processed data, contain pertinent leakage information related to the secret key. Third, the information associated with the secret key is spread in several neighboring sampling points with different degrees of leakages. We analytically derive the Key-leakage relevance factor for each clustered sampling point to quantify the degree of leakage associated with the secret key. Fourth, by means of Hebbian learning, a weight proportional to the Key-leakage relevance factor is updated iteratively based on the values of relevance factor and traces of the sampling points. The converged weights which are being assigned to clustered sampling points are linked to their associated PLI to further increase the correlation of the PLI with the processed data. Therefore, the required number of PLI measurements, to reveal the secret key, can be reduced significantly. In addition, we analytically show that the computational complexity of our proposed PRL is O(n) when compared to the reported profiling techniques having O(n(2)) and O(n(3)) computational complexities. Based on the experiments of our proposed PRL performed on the PLI of AES-128 algorithm, the results depicting that the sampling points of PLI are reduced 87 percent after the k-NN variance clustering. The converged weight with learning error rate < 1 percent is attained with only 538 iterations. The robustness of our proposed PRL is examined with four different frequencies (embodying four noise levels), various reported profiling techniques and two hiding countermeasures applied on the PLI (vertical and horizontal hidings). Our proposed PRL successfully reduce 94.53-to-98.19 percent of traces when performing at four different frequencies. Based on the hiding countermeasures applied on the PLI, the weights converge at 7,517 iterations and the SCA requires only 523 traces to reveal the secret key. By comparing with reported techniques which require > 10(6) traces, our proposed PRL is similar to 2,000 x more efficient in performing SCA.

Radio-Frequency Identification (RFID) tag-based applications are usually resource constrained and security sensitive. However, only about 2,000 gate equivalents in a tag can be budgeted for implementing security components [27]. This requires not only lightweight cryptographic algorithms such as PRESENT (around 1,000 gate equivalents) but also lightweight protections against modern Side Channel Attacks (SCAs). With this budget, the first-order masking and fault detection are two suitable countermeasures to be developed for PRESENT. However, if both countermeasures are applied without any optimization, it will significantly exceed the given area budget. In this work, we optimize area to include both countermeasures to maximize the security for PRESENT within this RFID area budget. The most area-consuming parts of the proposed design are the masked S-boxes and the inverse masked S-boxes. To optimize the area, we have deduced a computational relationship between these two parts, which enables us to reuse the hardware resource of the masked S-boxes to implement the inverse masked S-boxes. The proposed design takes up only 2,376 gates with UMC 65nm CMOS technology. Compared with the unoptimized design, our implementation reduces the overall area by 28.45%. We have tested the effectiveness of the first-order Differential Power Analysis (DPA) and Differential Fault Analysis (DFA) -resistant countermeasures. Experimental results show that we have enhanced the SCA resistance of our PRESENT implementation.

In-Vehicle Network (IVN) is composed of many communication nodes and Electronic Control Units (ECUs). The complex and interactive hybrid IVN expose more vulnerabilities of the system as it connects to the external network environment and opens up more attacking surface. In this paper, we first show a complete structure of the in-vehicle hybrid network. Then, we propose a three-layer network structure model, analyze the security threats of each layer, and compare the state-of-the-art countermeasures in detail. Finally, we identify the challenges and future research directions for the security of the in-vehicle hybrid network.

Improving the energy efficiency of on-chip SRAM is a crucial task in memory-intensive system designs. This paper presents design considerations and architectural exploration for energy-efficient data-dependent SRAMs, in which the power consumption depends on the data stored in the bitcells. We further categorize the data-dependent SRAM designs into two broad types, i.e., distance-based SRAM and weight-based SRAM, and point out similarities of such data-dependent power consumption mechanism between the SRAM designs and bus termination techniques. Simulation results in a commercial 40nm CMOS technology show that when more than 50%/25% of write/read data word are bit 1, the DD-8T SRAM is more energy-efficient than the 6T SRAM. And with XNOR encoded correlated image data, DD-8T SRAM shows both decreased write (1.4× to 2.4×) and read (1.64× to 1.85×) access energy compared to 6T SRAM.

Sensitive data are usually transferred within a vehicle using FlexRay protocol. To prevent the in-vehicle data from the manipulation and man-in-the-middle attacks through On Board Diagnostic (OBD-II) port, appropriate security schemes should be applied. In this paper, we propose a scheme to embed data integrity and confidentiality into the original FlexRay data frames and reuse the Cyclic Redundancy Check (CRC) field of existing FlexRay data frame to implement data integrity, which does not require to modify the current FlexRay protocol. We select a recently invented lightweight authenticated encryption scheme, AEGIS [5], to protect the dynamic frames, which achieves a shorter latency. We apply AES-CCM (Counter with CBC-MAC (CCM) [1]) to protect the static frames, whose latency is not stringent. We achieve a real-time 32-bit Message Authentication Code (MAC) for the static frames and an offline 64-bit MAC for the dynamic frames. In addition, we propose a unified architecture for implementing both AES-CCM and AEGIS, which reduces the required hardware resources. The experimental results show that our proposed design can achieve 3.71 Gbits/s and 9.44 Gbits/s for computing AES-CCM and AEGIS on automotive-grade XA Zynq-700 all programmable SoCs (XC7Z020), respectively. Compared to the state-of-the-art work of AES-CCM, our proposed design reduces 17.98% clock cycles.(1)

To secure the data stored in large-scale Storage Area Network (SAN) applications, high throughput Advanced Encryption Standard (AES) encryption and decryption are required. However, this solution may take up more hardware resources, which leads to unscalability for future needs. To solve this problem, we develop a high throughput and resource efficient AES encryption/decryption based on FPGA, which fully exploiting the dedicated resources of modern FPGAs, such as Block RAM (BRAM) and Digital Signal Processing (DSP) slices. We also propose a unified architecture for AES encryption and decryption. Furthermore, we move the map and the inverse map functions outside the AES encryption/decryption round. In order to shorten the critical path, we optimized the transformation matrix of the map function and its inverse transformation matrix. We use the same hardware resource to perform computations of both SubBytes and InvSubBytes, as well as computations of MixColumns and InvMixColumns. Finally, proper pipelined registers and DSP slices have been inserted into the proposed unrolling architecture to achieve high throughput. Experimental results show that our designs can achieve 78.22 Gbits/s using 5613 slices, 144 DSP slices without BRAM; or 68.44 Gbits/s using 4345 slices, 171 DSP slices with 400X36K BRAMs on XC6VLX240T FPGA.

Robust sensor system plays an important role in Internet of Things (IoTs). These intelligent sensors are required to be low cost and reliable, which provides confidentiality for private sensitive data. However, this protected system is still under the risk of Differential Fault Analysis (DFA) attacks. In this paper, we focus on DFA attacks to AES decryption as decryption receives the equalling importance as encryption. First, we induce a fault at the input of the third round in the procedure of AES decryption, in which w e successfully break it using one pair of fault-free and faulty plaintexts within 232 searching space. Then, we improve this attack by use of S-Box distribution table, which reduces the computational time from 853 ms to 70 ms on a dual Intel(R) Pentium(R) E6700 core (3.20 GHz). Compared to the existing work, our proposed attack reduces 79.5% computational time when both methods employ two pairs of fault-free and faulty ciphertexts/plaintexts.

There are many simulators to evaluate the performance of computer architecture, however they are commonly based on Software Architecture Model Execution (SAME). Due to hardly implement parallel execution on multicore platforms, their simulation speeds are slow. To solve the problem, we propose to improve simulation speed of SAME simulators on FPGA using SystemC synthesizable timing models. First, we need substitute the C++ timing model in the original x86 SAME simulator by our SystemC timing model. Second, we convert our SystemC timing model into Verilog timing model aided by Xilinx Vivado tool. Finally, we develop necessary components to support PCIe communication between the timing model running on FPGA (a Xilinx VC707 evaluation board) and the functional model running on the host machine, including a PCIe DMA controller and a PCIe driver. Our experiment results show that the proposed simulator is 47∼91 times faster than original x86 SAME simulator. In general, our work could provide a feasible solution for designers to improve the simulation speed of SAME simulators.