Embedded FPGA (eFPGA)-based hardware redaction has emerged as a promising technique for protecting the intellectual property (IP) of integrated circuits. Existing approaches select a subset of the logic at the register-transfer level (RTL) and replace it with a programmable eFPGA module. However, due to their lack of awareness of physical information, these approaches incur significant power, performance, and area (PPA) overhead on the resulting chip. This paper presents a physically guided partitioning approach that divides the original design into two parts: one implemented as an application-specific integrated circuit (ASIC) and the other redacted onto an embedded FPGA fabric. It leverages a graph neural network to encode both the structural and physical information of each gate into an embedding vector. It then employs a clustering and selection process to identify the redaction candidate. Experiments demonstrate that our approach consistently reduces timing overhead while achieving comparable or superior results in terms of area, security, and resource consumption.

A refinement relation captures the state equivalence between two sequential circuits. It finds applications in various tasks of VLSI design automation, including regression verification, behavioral model synthesis, assertion synthesis, and design space exploration. However, manually constructing a refinement relation requires an engineer to have both domain knowledge and expertise in formal methods, which is especially challenging for complex designs after significant transformations. This paper presents a rigorous and efficient sequential equivalence checking algorithm for non-cycle-accurate designs. The algorithm can automatically find a concise and human-comprehensible refinement relation between two designs, helping engineers understand the essence of design transformations. We demonstrate the usefulness and efficiency of the proposed algorithm with experiments and case studies. In particular, we showcase how refinement relations can facilitate error detection and correction for LLM-generated RTL designs.

Logic locking is a promising approach to protect the intellectual properties of integrated circuits. Existing logic locking schemes assume that an adversary must possess a cycle-accurate oracle circuit to launch an I/O attack. This paper presents DE2, a novel and rigorous attacking algorithm based on a new adversarial model. DE2 only takes a high-level functional specification of the victim chip. Such specifications are increasingly prevalent in the modern IC design flow. DE2 closes the timing gap between the specification and the circuit with an automatic alignment mechanism, which enables effective logic decryption without cycle-accurate information. An essential enabler of DE2 is a synthesis-based sequential logic decryption algorithm called LIM, which introduces only a minimal overhead in every iteration. Experiments show that DE2 can efficiently attack logic-locked benchmarks without access to a cycle-accurate oracle circuit. Besides, LIM can solve 20% more ISCAS'89 benchmarks than state-of-the-art sequential logic decryption algorithms.

As the toolbox of base editors (BEs) expands, selecting appropriate BE and guide RNA (gRNA) to achieve optimal editing efficiency and outcome for a given target becomes challenging. Here, we construct a set of 10 adenine and cytosine BEs with high activity and broad targeting scope, and comprehensively evaluate their editing profiles and properties head-to-head with 34,040 BE-gRNA-target combinations using genomically integrated long targets and tiling gRNA strategies. Interestingly, we observe widespread non-canonical protospacer adjacent motifs (PAMs) for these BEs. Using this large-scale benchmark data, we build a deep learning model, named BEEP (Base Editing Efficiency Predictor), for predicting the editing efficiency and outcome of these BEs. Guided by BEEP, we experimentally test and validate the installment of 3,558 disease-associated single nucleotide variants (SNVs) via BEs, including 20.1% of target sites that would be generally considered as "uneditable", due to the lack of canonical PAMs. We further predict candidate BE-gRNA-target combinations for modeling 1,752,651 ClinVar SNVs. We also identify several cancer-associated SNVs that drive the resistance to BRAF inhibitors in melanoma. These efforts benchmark the performance and illuminate the capabilities of multiple highly useful BEs for interrogating functional SNVs. A practical webserver (http://beep.weililab.org/) is freely accessible to guide the selection of optimal BEs and gRNAs for a given target.

Automatic diagnostic methods utilizing image analysis have seen a surge in development in recent years. However, achieving a comprehensive diagnosis necessitates considering clinical information. In the domain of skin disease, simply treating diagnosis as a multi-class image classification task poses inevitable bottlenecks. While existing methods incorporating Bayesian networks offer partial solutions, given the vast number of skin disease types, further integration with richer clinical information and diverse forms of deep neural networks would significantly escalate associated costs. This paper proposes an extensible diagnostic architecture. For newly added diseases and subsequently added clinical information, we integrate the output of deep neural networks into Bayesian networks more efficiently via semantic analysis. Through adjustments to node distribution types and the reduction of unnecessary connections, we expedite the development of a diagnostic system capable of addressing a wider range of skin diseases. Existing high-performing deep learning models, including multi-task and concept bottleneck, can be flexibly integrated into the system. Incorporating dermatologists’ expertise and reusing trained neural networks additionally reduces system development costs. At the same time, our architecture ensures excellent diagnostic accuracy. Through experiments leveraging the PAD-UFES-20 and SkinCon benchmarks, we have demonstrated that this architecture achieves a balanced diagnostic accuracy improvement of 19.3% over pure deep learning methods, with metrics including AUC surpassing those of existing published works. Our code can be accessed through the GitHub Repository: https://github.com/KevinInfinigon/MultimodalBayesianNetworks.

Deep neural networks are susceptible to model piracy and adversarial attacks when malicious end-users have full access to the model parameters. Recently, a logic locking scheme called HPNN has been proposed. HPNN utilizes hardware root-of-trust to prevent end-users from accessing the model parameters. This paper investigates whether logic locking is secure on deep neural networks. Specifically, it presents a systematic I/O attack that combines algebraic and learning-based approaches. This attack incrementally extracts key values from the network to minimize sample complexity. Besides, it employs a rigorous procedure to ensure the correctness of the extracted key values. Our experiments demonstrate the accuracy and efficiency of this attack on large networks with complex architectures. Consequently, we conclude that HPNN-style logic locking and its variants we can foresee are insecure on deep neural networks.

A globally robust deep neural network resists perturbations on all meaningful inputs. Current robustness certification methods emphasize local robustness, struggling to scale and generalize. This paper presents a systematic and efficient method to evaluate and verify global robustness for deep neural networks, leveraging the PAC verification framework for solid guarantees on verification results. We utilize probabilistic programs to characterize meaningful input regions, setting a realistic standard for global robustness. Additionally, we introduce the cumulative robustness curve as a criterion in evaluating global robustness. We design a statistical method that combines multi-level splitting and regression analysis for the estimation, significantly reducing the execution time. Experimental results demonstrate the efficiency and effectiveness of our verification method and its capability to find rare and diversified counterexamples for adversarial training.

In high-level design explorations, many useful optimizations transform a circuit into another with different operating cycles for a better trade-off between performance and resource usage. How to efficiently check their equivalence is critical and challenging since most existing equivalence checkers are designed for cycle-accurate circuits. This paper presents SE3, an efficient sequential equivalence checker without assumption on cycle-accuracy, latch mapping, or I/O interface of the checked circuits. It proves the equivalence of two circuits by computing an equivalence relation between the states of the two circuits and utilizes syntax abstraction to accelerate this process. Experimental results show that SE3 is significantly faster than state-of-the-art sequential equivalence checking algorithms.

Artificial intelligence aims to mimic human intelligence by giving machines the ability to perceive and think. However, current AI is on the horns of a dilemma. Tools like deep learning are good at finding similarities but cannot make reasonable inferences like humans. Their inability to integrate with human knowledge also requires large amounts of input data for tuning. In this paper, we propose an architecture that combines deep neural networks as nodes into Bayesian networks, which combines human knowledge with the perceptual results of deep learning tools. Using Bayesian networks for inference provides good interpretability and acceptable training data requirements. This architecture can correlate symptoms, demographic information, and deep neural networks in dermatological diagnosis. We conducted experiments on the ISIC 2019: Training dataset. With the help of dermatologists' expert knowledge, the architecture achieves an overall diagnostic accuracy of 88.1%, which is 23.6% higher than the pure deep learning approach.

With the rapid evolution of the IC supply chain, circuit IP protection has become a critical realistic issue for the semiconductor industry. One promising technique to resolve the issue is logic locking. It adds key inputs to the original circuit such that only authorized users can get the correct function, and it modifies the circuit to obfuscate it against structural analysis. However, there is a trilemma among locking, obfuscation, and efficiency within all existing logic locking methods that at most two of the objectives can be achieved. In this work, we propose ObfusLock, the first logic locking method that simultaneously achieves all three objectives: locking security, obfuscation safety, and locking efficiency. ObfusLock is based on solid mathematical proofs, incurs small overheads (<5% on average), and has passed experimental tests of various existing attacks.

Federated Learning is an emerging distributed collaborative learning paradigm used by many of applications nowadays. The effectiveness of federated learning relies on clients' collective efforts and their willingness to contribute local data. However, due to privacy concerns and the costs of data collection and model training, clients may not always contribute all the data they possess, which would negatively affect the performance of the global model. This paper presents an incentive mechanism that encourages clients to contribute as much data as they can obtain. Unlike previous incentive mechanisms, our approach does not monetize data. Instead, we implicitly use model performance as a reward, i.e., significant contributors are paid off with better models. We theoretically prove that clients will use as much data as they can possibly possess to participate in federated learning under certain conditions with our incentive mechanism

Abstract Research on establishing continuous cell line (CCL) has gained much attention recently, especially for its promising usage as an alternative substrate for vaccine production. In order to set up a ready-for-use protocol for potentially immortalizing animal originated cells, this study used MDCK as the pilot cells to explore the method using hTERT and SV40-LT genes transfected through liposome and lentivirus. Results showed that hTERT transfection with liposome and lentivirus, and SV40-LT with lentivirus could be successfully expressed in MDCK cells. Transfection efficiency of lentivirus was higher than liposome, and SV40-LT was easier to induce cell proliferation than hTERT. No mutation occurred during the passage and the original phenotype was maintained. The study provided a reference and potential method for the subsequent immortalization of primary cells.

Availability and security problems in cellular emergency call systems can cost people their lives, yet this topic has not been thoroughly researched. Based on our proposed Seed-Assisted Specification method, we start to investigate this topic by looking closely into one emergency call failure case in China. Using what we learned from the case as prior knowledge, we build a formal model of emergency call systems with proper granularity. By running model checking, four public-unaware scenarios where emergency calls cannot be correctly routed are discovered. Additionally, we extract configurations of two major U.S. carriers and incorporate them as model constraints into the model. Based on the augmented model, we find two new attacks leveraging the privileges of emergency calls. Finally, we present a solution with marginal overhead to resolve issues we can foresee.

Model checking techniques can verify correctness properties by exhaustively traversing the state space of a formal model. A large number of works [1, 4, 5] done by networking researchers use model checking. Each of the works comes with one or more formal models, which constitutes a valuable asset for the networking security research community. Nevertheless, we find these works do not fully exploit the potentials of their models.

Supervised learning on Deep Neural Networks (DNNs) is data hungry. Optimizing performance of DNN in the presence of noisy labels has become of paramount importance since collecting a large dataset will usually bring in noisy labels. Inspired by the robustness of K-Nearest Neighbors (KNN) against data noise, in this work, we propose to apply deep KNN for label cleanup. Our approach leverages DNNs for feature extraction and KNN for ground-truth label inference. We iteratively train the neural network and update labels to simultaneously proceed towards higher label recovery rate and better classification performance. Experiment results show that under the same setting, our approach outperforms existing label correction methods and achieves better accuracy on multiple datasets, e.g.,76.78% on Clothing1M dataset.

Logic encryption has attracted much attention due to increasing IC design costs and growing number of untrusted foundries. Unreachable states in a design provide a space of flexibility for logic encryption to explore. However, due to the available access of scan chain, traditional combinational encryption cannot leverage the benefit of such flexibility. Cyclic logic encryption inserts key-controlled feedbacks into the original circuit to prevent piracy and overproduction. Based on our discovery, cyclic logic encryption can utilize unreachable states to improve security. Even though cyclic encryption is vulnerable to a powerful attack called CycSAT, we develop a new way of cyclic encryption by utilizing unreachable states to defeat CycSAT. The attack complexity of the proposed scheme is discussed and its robustness is demonstrated.

short-paper Share on CellScope: Automatically Specifying and Verifying Cellular Network Protocols Authors: Yinbo Yu School of Electronic Information, Wuhan University, China and Department of Computer Science, Northwestern University, USA School of Electronic Information, Wuhan University, China and Department of Computer Science, Northwestern University, USAView Profile , You Li Department of Computer Science, Northwestern University, USA Department of Computer Science, Northwestern University, USAView Profile , Kaiyu Hou Department of Computer Science, Northwestern University, USA Department of Computer Science, Northwestern University, USAView Profile , Yan Chen Department of Computer Science, Northwestern University, USA Department of Computer Science, Northwestern University, USAView Profile , Hai Zhou Department of Computer Science, Northwestern University, USA Department of Computer Science, Northwestern University, USAView Profile , Jianfeng Yang School of Electronic Information, Wuhan University, China School of Electronic Information, Wuhan University, ChinaView Profile Authors Info & Claims SIGCOMM Posters and Demos '19: Proceedings of the ACM SIGCOMM 2019 Conference Posters and DemosAugust 2019 Pages 21–23https://doi.org/10.1145/3342280.3342294Published:19 August 2019Publication History 2citation228DownloadsMetricsTotal Citations2Total Downloads228Last 12 Months25Last 6 weeks4 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Cyclic logic encryption is newly proposed in the area of hardware security. It introduces feedback cycles into the circuit to defeat existing logic decryption techniques. To ensure that the circuit is acyclic under the correct key, CycSAT is developed to add the acyclic condition as a CNF formula to the SAT-based attack. However, we found that it is impossible to capture all cycles in any graph with any set of feedback signals as done in the CycSAT algorithm. In this paper, we propose a behavioral SAT-based attack called BeSAT. Be-SAT observes the behavior of the encrypted circuit on top of the structural analysis, so the stateful and oscillatory keys missed by CycSAT can still be blocked. The experimental results show that BeSAT successfully overcomes the drawback of CycSAT.

Logic encryption is a powerful hardware protection technique that uses extra key inputs to lock a circuit from piracy or unauthorized use. The recent discovery of the SAT-based attack with Distinguishing Input Pattern (DIP) generation has rendered all traditional logic encryptions vulnerable, and thus the creation of new encryption methods. However, a critical question for any new encryption method is whether security against the DIP-generation attack means security against all other attacks. In this paper, a new high-level SAT-based attack called SigAttack has been discovered and thoroughly investigated. It is based on extracting a key-revealing signature in the encryption. A majority of all known SAT-resilient encryptions are shown to be vulnerable to SigAttack. By formulating the condition under which SigAttack is effective, the paper also provides guidance for the future logic encryption design.

Though firewall and IDS (Intrusion Detection System) are used to filter the accessing traffic for network security, they still cannot ensure to protect the key files of network system from being corrupted by advanced and sophisticated attack, such as hacker's stealthy penetration and worm's wide spread by attaching itself to E-mail. The framework of an automatic-recovery security model is presented based on the allied backup of key files; it ensures that the network system can deliver essential services despite being attacked because it monitors key files and recovers corrupted files automatically and quickly. This paper explains how to recover a corrupted file quickly through locating one ally, whose file corresponding to that corrupted file remains uncorrupted, and using that uncorrupted file to implement quick recovery. The simulation results show that our automatic-recovery security model based on allied backup of key files is effective and efficient and can meet the requirements of intrusion tolerance and survivability.