Multi-bit flip-flop (MBFF) banking and debanking is a widely adopted technique for optimizing power and total negative slack (TNS) during the post-placement stage of digital design. While banking flipflops can reduce both power and area, excessive banking may lead to increased TNS due to significant register displacement, as well as bin density violations (BDVs) caused by over-placing MBFFs in legalized regions. To address these challenges, the EDA community recently organized a CAD Contest seeking innovative solutions from both academia and industry. In response, we present TIMBER, a fast and effective optimization algorithm that balances competing objectives in MBFF placement. Unlike existing methods, TIMBER employs a bin-density-aware placement strategy that simultaneously minimizes BDVs and TNS, while also achieving gains in power and area efficiency. To further enhance the runtime performance, TIMBER incorporates a parallelization strategy. Experimental results on the official 2024 CAD Contest benchmarks demonstrate that TIMBER outperforms the first-place winner, delivering on average $13.08 \times$ better solution quality, zero BDVs, $5.06 \times$ faster single-threaded runtime, $3.56 \times$ lower memory usage and up to $72.49 \times$ speedup in multi-threaded execution.
Hyperspectral images (HSIs) provide unparalleled spectral detail for material analysis across diverse fields, but their high data dimensionality challenges real-time processing. Coded Aperture Snapshot Spectral Imaging (CASSI) addresses this problem by compressing 3D spectral information into a single 2D snapshot, but it introduces an ill-posed reconstruction problem. In response, numerous effective methods employ Deep Unfolding Networks (DUNs), which combine data modules and prior modules to improve reconstruction quality. However, multihead attention in prior modules causes significant storage and computational overhead, while redundant operations in data modules further reduce computational efficiency. To efficiently deploy DUNs on edge devices, this paper proposes an algorithmhardware co-optimization framework for hyperspectral image reconstruction. First, a lightweight attention-free DUN prior module, Lightweight Spectral Prior (LSP), is designed. Second, a precision-scalable hardware architecture is developed to accelerate the DUN data module, which features a stage-wise bit-width allocation to enhance processing efficiency. Experimental results demonstrate that our algorithm achieves superior reconstruction quality compared with recent state-of-the-art methods. The hardware design for the data module is implemented on the Xilinx ZU19EG FPGA evaluation board. In FPGA-GPU heterogeneous system execution, we achieve up to $2.3 \times$ speedup in inference compared with GPU-only execution.
Synthesized netlists often leave substantial room for area optimization due to the limited function diversity in standard cell libraries, which frequently results in recurring logic patterns that could be compacted through cell combination-referred to as hypercells in this work. While prior studies have demonstrated the potential of hypercell-based optimization, most lack efficient and scalable mining strategies. We present SOFA-H, a post-synthesis framework that extracts and remaps hypercells for maximum area reduction. SOFA-H (i) mines fanout-induced subgraphs and canonically encodes them using P-Representatives, (ii) selects an optimal set of hypercells with non-overlapping replacements via a one-shot weighted MaxSAT formulation, and (iii) supports high input, multi-output cells with scalable runtime. Evaluated on the EPFL benchmark suite synthesized using FreePDK45 and ASAP7, SOFA-H achieves average area reductions of 12.2% and 7.4%, respectively, and runs $380 \times$ faster on average at ASAP7 compared to the state-of-the-art method. These results demonstrate that the extracted hypercells offer a scalable and effective path to closing the area gap left by conventional synthesis.
Timing behavior of standard cells is represented as two-dimensional tables in a timing library, where each table entry is obtained through transistor-level simulation. As technology scales, the number of design corners and standard cells has increased dramatically, leading to a substantial increase in simulation time for timing characterization. This may delay the design schedule or impose additional demands on tool licenses. To address this challenge, we propose a fast timing characterization method that selectively uses transistor-level simulation and model-based prediction. In this method, a subset of table entries is obtained through simulation, while the remaining entries are predicted by regression models trained on the simulated data. Multiple regression models are employed to capture the diverse characteristics of each entry location, and the most accurate model for each entry is identified at one corner, called an anchor corner. The selected models are then used to predict the corresponding entry at target corners. Experimental results show that the proposed method achieves high accuracy with a 40% reduction in runtime; the mean and 3-sigma absolute errors are 0.4% and 2.3%, respectively, representing a significant improvement over conventional methods. The accuracy of the proposed method is further validated on 7-nm technology libraries.
While copy-on-write file systems like Btrfs seem well-suited for zoned namespace SSDs (ZNS) due to out-ofplace updates, we find that Btrfs worsens the performance interference ZNS aims to mitigate. Its proactive zone reclamation causes substantial CPU and I/O overhead, severely degrading performance under write-intensive workloads. To address this, we propose a new Btrfs space management design incorporating a metadata marking strategy to predict near-term metadata deletions, a recycling urgency metric to prioritize block-group reclamation, and dynamic metadata placement guided by urgency and marking states. Our approach improves sustained-write performance by over 22% compared with the original Btrfs on average and up to 65% over Btrfs configured for aggressive reclamation during degradation periods.
Advanced edge artificial intelligence (AI) chips need to balance flexible computation, high energy efficiency, and sufficient inference accuracy across diverse workloads. Many compute-in-memory (CiM) designs enable efficient neural network acceleration but focus solely on integer (INT) multiply-and-accumulate (MAC) operations, limiting precision. Some CiM macros add extra circuitry to support floating point (FP) MACs, but these dedicated exponent-handling blocks often waste area when running INT workloads. In this paper, we propose CDACiM, a charge-domain CiM macro that supports both FP and INT MAC operations with minimal overhead. CDACiM introduces a reconfigurable capacitor digital-to-analog converter (RCDAC) that performs both exponent summation and bitwise AND for mantissa multiplication. To calculate exponent offsets, we develop a shared single-slope ADC (SS-ADC) that finds the maximum exponent and computes differences in time domain simultaneously. Our design includes a sparsity-aware computation scheme with tunable thresholds that skips low-importance input-weight pairs, boosting energy efficiency through higher input sparsity. We also introduce a multi-bit input accumulation method that leverages ADC redundancy during quantization and normalization to improve performance. Implemented in a 40nm CMOS process, CDACiM demonstrates an excellent flexibility and trade-off between accuracy and resource usage. Notably, it is the first CiM design to reconfigure capacitor-based INT macro for parallel exponent computation. CDACiM achieves 16.2 TOPS/W for INT MACs and $\mathbf{1 5. 9}$ TFLOPS/W for FP MACs. It delivers a $\mathbf{1. 3 6 - 1. 4 8 \times}$ improvement in energy efficiency with minimal accuracy loss compared to recent FP CiM macros.
In-memory search has emerged as a promising solution for efficient vector discovery of the nearest neighbors in general-purpose vector databases. However, templated storage-in-array structure and VMM-based computational form of inmemory search pose challenges in supporting generic distance computations. In this work, we introduce a novel memristive in-memory similarity measure engine, MemSearch, for configurable distance calculations, including dot distance, ED, and CD. MemSearch highlights two aspects: data storage and distance computing. For data storage, we propose a Unified Similarity Element Mapping (USEM) scheme based on a pair array to accommodate various similarity calculations. For distance computing, we introduce a Reconfigurable Current Computing (RCC) circuit designed to process multiple arithmetic rules in similarity calculations, with a slightly increase of 4.4% and 9.9 % in energy consumption for ED and CD, respectively. We have tested various datasets with different modalities, including images, voice, human activity and text. Experimental results demonstrate that the MemSearch engine achieves improvements of $864 \times, 802 \times$, and $1474 \times$ in energy efficiency over CMOS-based engines for dot distance, ED, and CD calculations, respectively. The MemSearch engine highlights its potential for future highly efficient general-purpose in-memory vector databases.
Cardiovascular diseases remain a leading global health threat, with arrhythmia being a key early indicator of cardiac abnormalities. The need for continuous cardiac monitoring has driven demand for portable, low-power arrhythmia detection systems. This paper presents a low-power mixed-precision System-on-Chip (SoC) solution designed for arrhythmia detection using 12-lead electrocardiogram (ECG) signals. The proposed approach employs a dynamically reconfigurable convolutional neural network (CNN) architecture with flexible hyperparameters, enhancing hardware adaptability while reducing resource overhead and power consumption. At the computation level, an 8-bit and 16-bit mixed-precision floating-point multiplier is introduced to effectively balance arithmetic accuracy and energy efficiency. Furthermore, clock gating and multi-threshold voltage techniques are employed at the digital back-end to further reduce the power consumption of the chip. Through system-level and module-level optimization, the proposed chip design is of great significance for enabling low-power arrhythmia detection in power-constrained portable medical devices.
With the rise of fabless manufacturing, the risks of piracy and overproduction in integrated circuits have become more pressing, making it crucial to analyze and prevent hardware-based attacks. Although existing machine learning oracle-less attacks on logic-locked circuits are able to report approximate keys, they often struggle to produce operationally effective keys because they focus mainly on the structural topology of the circuits. This paper addresses this limitation by incorporating both functional features, such as output corruptibility, and behavioral features, like power consumption and area overhead, into graph neural network-based circuit modeling attacks. With the help of both subgraph-level and graph-level attack strategies, we achieve notable improvements in rendering a meaningful key compared to existing oracleless methods. In addition, our graph-level model is explainable, providing insights into the learning process and how the attack is executed. These findings are critical for chip design houses looking to identify and address security vulnerabilities, ultimately safeguarding hardware intellectual property.
Scheduling is a key aspect in mapping applications to coarse-grained reconfigurable architectures (CGRA). During scheduling, the number of pipeline registers on each path is determined to ensure that the data for an operation arrives at the correct cycle. Traditional scheduling methods, such as as soon as possible (ASAP) and as late as possible (ALAP), determine the pipeline registers without considering the placement of operations. This can restrict the mapping algorithm, forcing placement to accommodate scheduling and limiting routing options to satisfy both scheduling and placement. To overcome the limitations of traditional schedulers, we propose a method that adaptively adjusts the schedule during the initial routing phase. In this approach, the mapping algorithm begins with an ASAP schedule to establish initial schedule constraints. We then utilize simulated annealing for placement, and we employ a architecture-responsive scheduling algorithm post-placement to update the schedule of each edge based on the placement and generate an initial routing solution with overlaps. Afterwards, the PathFinder algorithm is applied to the initial routing solution, along with the generated schedule, to find a valid routing with no overlaps. Our results demonstrate that the architecture-responsive scheduling approach maintains a quality comparable to that of conventional ASAP scheduling. Furthermore, architecture-responsive scheduling enables generic mapping of applications onto restricted architectures that do not allow routes to bypass pipeline registers, a challenge that traditional schedulers do not address.
Logic locking, which ensures that a logic circuit operates correctly only when the correct key is input, has gained attention as a countermeasure against the infringement of hardware intellectual property and reverse engineering threats. However, many existing methods have been compromised by SAT attacks. Recent research has reported that multi-key logic locking methods are effective as a fundamental countermeasure against SAT attacks. However, these methods face major issues, such as limitations in their application scope and increased overhead when applied. We propose LumiLock, a novel LUTbased multi-key logic locking method, to fundamentally address these issues. LumiLock strategically hybridizes LUT-based and multi-key techniques, employing a unique mechanism with static and dynamic input-dependent keys. This approach fundamentally disrupts SAT solvers’ ability to identify consistent distinguishing input patterns, thereby preventing key extraction. Evaluation against 10 types of SAT attacks on ISCAS’85, ISCAS’89, and ITC’99 benchmarks demonstrates LumiLock’s robustness. It consistently resists all tested attacks across both combinational and sequential circuits, where conventional multi-key methods are inapplicable. Furthermore, LumiLock achieves this strong security with optimized overhead, including a smaller key size compared to other state-of-the-art multi-key schemes.
Proximity inductive coupling interfaces provide a low-cost, high-yield solution for 3D assembly, thanks to their compatibility with standard CMOS processes. However, they suffer from challenges related to the design complexity of both the coil and the receiver. To address these issues, this work proposes a comprehensive approach that includes an analytical coil design methodology applicable to edge-coupled configurations, an oblong coil structure to improve layout efficiency, and a standard-cell-based receiver architecture that enables simplified and scalable implementation. The proposed oblong coil achieves a 4.5 times improvement in area efficiency compared to traditional square coils, while maintaining adequate coupling strength and crosstalk tolerance, as validated through a test chip fabricated in a 40 nm CMOS process. The proposed receiver leverages bias sharing and a digitally tunable, standard-cell-based hysteresis comparator, resulting in 0.23 times the area and 0.37 times the energy consumption relative to a conventional analog comparator, as confirmed through simulations in a 16 nm FinFET process.
Engineering Change Order (ECO) is the task of finding the non-intrusive design implementation updates to comply with a specification revision. This paper states the rectification problem in quantified Boolean logic that gives sound and complete capture of the update choices for an ECO. Its closed-form statement offers an analytical search for small patches that maximize logic sharing in the implementation. With the abstraction-refinement paradigm assisted by relevance classification, we effectively generalize the sampled knowledge of a revision, enabling the identification of compact updates without undue computational costs. Our experimental evaluation demonstrates almost twice as few gates in synthesized patches compared to the reported state-of-the-art results.
Multi-corner timing analysis is essential for ensuring the robustness of circuits under variations in process, voltage, and temperature (PVT). Along with clock skew scheduling, delay padding is used to address hold violations. However, applying padding consistently in multiple corners is challenging due to conflicting constraints and the prevalence of “ping-pong” effects. This paper presents a novel methodology that uses dual decomposition to tackle this challenge. The problem is divided into a set of network flow problems, one for each corner. These problems are coupled through shared delay variables. Coordinating these subproblems using Lagrange multipliers ensures consistent padding assignments across corners. Additionally, traditional padding methods often struggle with physical feasibility. The incorporation of path relationship analysis is proposed to identify viable, physically feasible padding locations. Experimental results on industrial benchmarks demonstrate that the proposed method efficiently identifies feasible padding solutions and achieves the minimum clock period that satisfies the setup and hold time constraints for all corners. Compared to the single worst-case corner baseline, the optimized clock period is reduced by up to 9%, highlighting the effectiveness of our approach.
Macro placement critically influences physical design quality, yet optimizing timing characteristics at this stage remains a challenging research frontier. In this paper, we propose a novel timing-driven macro placement framework comprising two major components: a global macro placement approach and an incremental macro placement refinement approach. Our global placement begins by applying Hier-RTLMP’s multilevel autoclustering engine to group cells into clusters. Each cluster is abstracted as a density-inflated pseudo macro, and an analytical method is applied to generate the initial top-level layout. Then, intra-group macro placement is guided by dataflow-based virtual connection and solved via an integer-linear programming (ILP) approach. Each macro group (macros within the same cluster) is subsequently abstracted as a bounding box and placed via boundary-aware optimization followed by legalization. To further enhance macro placement quality, we develop an incremental refinement method applied after standard cell placement. It consists of two specialized strategies: array-constrained macro swapping and projected gradient descent (PGD)-based free macro shift, both targeting critical path slack improvement. We compare our framework with the state-of-the-art macro placer Hier-RTLMP on 15 benchmark suites from ChiPBench. For 7 designs employing both global macro placement and incremental refinement, our approach improves worst negative slack (WNS) and total negative slack (TNS) by 46.4% and 19.8%, respectively. For the remaining 8 designs that do not require incremental refinement, our approach improves the WNS and TNS by 24.5% and $\mathbf{2 8. 7 \%}$, respectively.
Implicit neural representations (INRs) have revolutionized signal encoding by using neural networks to map coordinates to signal attributes. Despite their success, INRs present significant hardware implementation challenges due to complex activation functions and floating-point operations. Unlike previous efforts, such as model pruning or quantization, we address these challenges by introducing AIRFSC, a novel activationfree stochastic computing (SC) architecture that leverages finitestate machines (FSMs). AIRFSC eliminates complex activation functions and processes data efficiently through stochastic bitstreams. Our approach decomposes the input signal into a series of Fourier basis functions, enabling the FSM-based architecture to learn smooth coordinate-to-attribute mappings for accurate signal reconstruction. Extensive experiments on diverse signal types demonstrate that AIRFSC achieves reconstruction quality comparable to state-of-the-art (SOTA) INRs implemented with multi-layer perceptrons (MLPs), while significantly improving hardware efficiency. Specifically, AIRFSC reduces power and area by $\mathbf{9 6. 8 \%}$ and $\mathbf{7 2. 8 \%}$ compared to Sinusoidal Representation Networks (SIREN), and by 97.9% and 81.3% compared to Wavelet Implicit Representation (WIRE).
Modern data centers increasingly use multi-GPU systems for AI and high-performance computing, where growing data transfer demands lead to high energy consumption and performance bottlenecks in electrical networks. Optical interconnects offer compelling advantages to address these challenges, including high bandwidth, distance-independent latency, and better energy efficiency. This paper presents DOME, a rack-scale optical interconnection network that connects multiple GPUs using high-radix optical switches and extends optical interfaces into GPU packages close to memories and multiprocessors, forming distinct in-GPU and GPU-to-GPU network domains. To efficiently manage the paths across switches and domains, we develop a multi-switch arbitration scheme and a time-slotted path reservation scheme that quickly identifies the earliest time when the path is available in all network domains, reducing unnecessary reservation retries. Evaluations reveal that DOME achieves 14% speedup while maintaining comparable energy consumption compared to the state-of-the-art preemptive chain feedback control scheme.
