As Moore’s Law tends to reach its limits, shrinking process technology nodes is no longer the most effective way to improve the performance of systems, and more attention is being focused on advanced packaging. Thermal dissipation as the main issue severely limits the reliability of 3D stacked modules. Embedded cooling is a feasible solution for interlayer cooling. However, the current manifold is incompatible with advanced packaging processes due to the footprint and manufacturing process. In this work, a manifold microfluidic cooling structure for embedded silicon Fan-Out (MMC-eSiFO) package is proposed and the thermal test vehicle (TTV) is designed, fabricated and tested. A silicon-based interposer is formed using a wafer bonding process by etching a cavity structure and a manifold channel on two silicon wafers, respectively. The large-area high-power chip is embedded into the cavity for effective cooling by the embedded microchannels. A high-density redistribution layer (RDL) is used to fan out the electrical I/O after fabricating the dielectric layer on the surface. In addition, multi-layer embedded liquid cooling of 3D package structure can be achieved by interposer with through silicon vias (TSVs). The use of a silicon-based interposer not only enables high aspect ratio TSVs and high-density RDL but also helps to reduce thermal stress in the package structure, as the interposer material is the same as the IC chip material. It is worth noting that the fabrication of the interposer and fan-out layer is wafer-level processing that enables production at scale. Multiple sets of cavities and manifold channels can be etched in a single package structure, making it compatible with chiplet technology. The package structure is expected to solve the thermal dissipation problem of multi-layer multi-chip assemblies.

Heat fluxes of GaN-based high electron mobility transistors (HEMTs) can reach dozens of kilowatts per square centimeter, and the heat is generated only within a small area with feature size of micrometer to millimeter length scales, which poses a huge challenge for thermal management. In this study, an embedded microfluidic cooling solution is proposed to dissipate heat from the hotspots, and thermal test vehicles are fabricated using the Micro-Electro-Mechanical System (MEMS) process. Cooling performances of hotspots with sizes ranging from 40 x 40 mu m(2) to 500 x 500 mu m(2) and varying locations are demonstrated. Thermal resistances of the test samples are analysed and the heat transfer coefficient can achieve 1.5 x 10(5) W/(m(2).K) using embedded microchannel cooling. We propose a compound plate spreading thermal resistance model to demonstrate the effect of the dielectric layer and the size of the heat source on heat dissipating capability of the microfluidic cooling system. Based on the thermal spreading model, when the heat source is small, integrating high thermal conductivity materials near the heat source can reduce its total thermal resistance by two orders of magnitude. By balancing the heat spreading resistance with the convective resistance of microchannel cooling, we find that similar to 1 mm can be considered as the critical length for distinguishing the primary thermal management approach for different sized hotspots. This paper provides useful design guidelines for embedded microchannel cooling of devices with localized heat generation patterns, such as HEMT devices.

随着集成电路制程趋于极限,登纳德缩放定律逐步失效,芯片的功率密度逐渐提升,尤其是在5G、物联网以及高性能计算快速发展的驱动下,单芯片面积也在增大,热耗散问题日趋严重,传统的冷却方式已无法保证芯片的可靠工作.将热沉制备在芯片内部可以避免封装材料的导热热阻和多层界面热阻,提升冷却性能和冷却效率.学术界针对芯片的嵌入式微流体冷却开展了大量卓有成效的研究和探索,不断提出新型通道结构设计方案,包括平行长直通道、歧管通道、射流通道等.旨在于优化泵功和热阻,在小压降下实现高效冷却.然而,随着芯片面积的增大,在限域空间实现高效冷却将更加困难,工艺难度和制造成本限制了嵌入式液冷的大规模商业化使用,目前在实际IC芯片内演示的冷却方案验证了嵌入式冷却的性能,但复杂度高,兼容性差,冷却性能有待进一步提升.尤其是在3D封装架构下,需要提出兼容小型化、高密度封装的通道结构,通过协同设计,在保证电学互连的前提下实现层间冷却.在优化通道结构设计的同时,还需要简化工艺,降低成本,提升嵌入式微流体冷却的工艺可靠性和长期工作可靠性,才能推进嵌入式微流体冷却技术的实际应用.

The power density of advanced electronic modules in the fields of RF microsystems, high-performance computing, has exceeded the order of kW/cm(2), which poses severe challenges to the efficient heat dissipation ability of modules. Manufacturing embedded microchannels in electronic modules through MEMS process to obtain high-efficiency liquid cooling heat dissipation capabilities is an important technical way to break through the "thermal bottleneck". The embedded microchannel brings efficient heat dissipation capabilities, but also brings unprecedented reliability challenges, due to its working environment with high temperature and pressure. In its long-term service, processes such as particle erosion, corrosion and clogging or fouling may occur, resulting in excessive stress, chip warpage, liquid leakage, etc., which affect the heat dissipation performance and cause chip failure. In this paper, the highly accelerated temperature and humidity stress testing, temperature shock testing and shear strength tests were carried out to evaluate the structural reliability of the gold-tin eutectic bonded PCB manifold and microchannel. The bonding interface was studied by X-ray before and after the test, which showed the bonding interface has no significant change, while the interface shear strength decreased. In addition, temperature cycling experiments were performed under working fluid flow conditions and changes in heat dissipation performance were detected. The results show that under the volume flow rate of 300 similar to 700 mL/min, considering the influence of experimental error, the thermal resistance and temperature rise of the sample are basically unchanged. As far as we know, there are currently no studies in the world in this regard. This work has important implications for advancing the practical application of embedded microchannel cooling.

以GaN为代表的新一代半导体材料具有宽禁带、高电子饱和速率、高击穿场强等优异的电学性能，使得射频、电力电子器件有了具备更高功率能力的可能，目前限制器件功率提升的主要瓶颈是缺少与之匹配的散热手段。具有极高热导率的金刚石已成为提升器件散热能力的重要材料，学术界针对金刚石与功率器件集成的先进热管理技术已经开展了大量有益的研究与探索，但是由于金刚石具有极强的化学惰性和超高的硬度，在实际集成和工艺加工过程中，金刚石-GaN界面容易出现热性能和可靠性问题，甚至会导致器件失效。对金刚石热管理技术的研究进展和存在的问题进行了深入分析，并对未来主要工作方向做了展望。

Embedded microfluidic cooling improves cooling efficiency by avoiding interfacial thermal resistance. However, the temperature rise of the fluid along the flow direction leads to an uneven axial temperature of the straight parallel microchannels (SPMCs), which then causes the degradation of microfluidic cooling uniformity, especially at the outlet position with the greatest thermal resistance. Counterflow microchannels (CFMCs) heat exchangers can be realized by adjusting the flow direction of adjacent channels to the opposite direction. In this paper, a one-dimensional thermal resistance model of CFMCs heat exchangers is established, and the surface temperature distribution characteristics of heat exchangers are studied. Under the assumption of a constant convective heat transfer coefficient, the equivalent neutral plane and the equivalent adiabatic line are defined, and the temperature distribution of the heating surface is analyzed by using the temperature rise characteristics of the working fluid after heat absorption. Both theoretical and numerical results show a quadratic distribution of the surface temperature in CFMCs. Compared with the SPMCs, CFMCs result in a higher average surface temperature but a lower maximum surface temperature, while the temperature standard deviation is reduced by more than 60%.

Dissipation of ultrahigh heat fluxes is critical to modern electronic chips as they become ever more compact and powerful. Here, by employing a systematic numerical study, we present a highly-efficient embedded single-phase water-cooled silicon heat sink featuring a manifold with interdigitated inlets and outlets and jet microchannels with sawtooth side walls. Compared to straight channels, the sawtooth walls reduce blockage of the jet inflow and therefore the pressure drop. Meanwhile, the sawtooth profile helps suppress the large recirculation region around the jet inlet and generate small vortices near the channel walls which facilitate fluid mixing and enhance heat exchange. This simultaneous enhancement of heat transfer and reduction of pressure drop leads to some of the highest cooling efficiencies. In particular, for a 3 x 3 mm 2 chip at a temperature rise of 60 K, dissipation of heat fluxes over 2100 W cm -2 is possible with a pumping power of about 1.3 W cm -2 . For heat fluxes around 10 0 0 W cm -2 , the coefficient of performance can reach beyond 20,0 0 0. In addition to the high performance, our heat sink can in principle be manufactured via standard silicon microfabrication technology.(c) 2023 Elsevier Ltd. All rights reserved.

This paper proposes a Ku-band cavity antenna for integrated packaging. The whole structure uses glass with micro-grooves as the substrate, and SOG and Parylene-N film on the upper part forms a cavity structure. The antenna pattern is fabricated on top of the film. The ground plane is on the bottom of a glass substrate. The optimized antenna has a thinner thickness and higher radiation performance. The antenna has a maximum gain of 9.6 dBi and an impedance bandwidth of 0.17 GHz. An all-glass antenna is designed for a comparative study, and it is found that the maximum gain of the design in this paper can be increased by 39%.

The thermal management of high power electronics is a serious problem thanks to developing the advanced semiconductor process and utilizing the new generation semiconductor materials. This paper designed and fabricated a thermal management system for high-power devices. The size of the system is only 45mm×45mm×5mm, and four chips with embedded microchannel were integrated into it. The experimental result shows that the system can dissipate 3020W heat power. The numerical simulation results also hint at the possibility of the thermal resistance up to 0.015 K/W at the flow rate of 1600 mL/min. This research explains the powerful potential of embedded cooling technology in high-power applications.

Since the embedded microchannel heat sink has become a potential thermal management technology developed for the next generation of power devices to ensure the reliability of the embedded microchannel chip. The finite element simulation technology was used to investigate the influence of different shapes of liquid inlets and outlets of the embedded microchannel chip during the flip-chip bonding process and carried out experiments to prove the simulation prediction. The results show that the optimized design of the shapes of liquid inlets and outlets can effectively reduce the stress performance of the chip. The maximal thermal stress of chips will decrease by more than 70 %. To the best of our knowledge, there is currently no research report in this area in the world. This work is of great significance in promoting the practical application of microfluidic chips.

Driven by the demands of the intelligent industry, integrated circuit chip has witnessed development in the direction of use of increased number of transistors and larger area. Consequently, power dissipation is increasingly limiting chip performance. In this study, an embedded microfluidic cooling solution for a 20 mm×20 mm high-power chip was realized. The microchannels and the double H type manifold channels were etched on two silicon wafers, and thereafter assembled employing the silicon-silicon direct bonding process. The depth of all the channels was 250 μm, and the width of the microchannels and manifold channels were approximately 210 μm and 2 mm after careful numerical optimization, respectively. In addition, a compact channel layout was used to enable cooling of the entire area. Platinum serpentine resistors were prepared for heating and temperature sensing, respectively. The global temperature was measured under a heat dissipation power of 417 W, the average temperature rise was 22.2 K, and the coefficient of performance was 3200 when using deionized water as the working fluid at the volume flow rate and pump pressure of 612 ml/min and 35.0 kPa, respectively. The average temperature rise agreed with the simulation results within 1.6 K. Moreover, this study proposed a simplified thermal resistance network model to examine the fin effects of the silicon substrate in the microchannels. The relationships between the Nusselt number and the Reynolds number were calculated for further optimization of channels. The proposed compact double H type manifold microchannels was concluded to be a promising embedded microfluidic cooling approach for large area high power chips.

The heat dissipation of power amplifier (PA) chips is one of the biggest challenges in the development of miniaturized state of art glass-based high-power RF modules. Glass has excellent electrical properties, but the extremely poor thermal conductivity of it also brings many barriers in the application. Its (quartz glass) thermal conductivity is only 1/93 of that of silicon, so there will be a problem of poor heat dissipation. In recent years, there has been an increasing amount of literature on microfluidic cooling technology and this method was demonstrate as an efficient way in cooling application. In this article, we designed, fabricated, and tested a Si-Glass microchannel heat sink, which took advantage of the high thermal conductivity of silicon to deal with the insufficient thermal conductivity of the glass interposer. Finite element simulation was used to study the thermal property of the Si-Glass heat sink and a multi-parameter optimal method was used to design the geometrical parameters, including the number of flow channels and other geometrical parameters of the heat sink. Then the aforementioned microchannel heat sinks were fabricated using cleanroom fabrication on 4-inch silicon and glass wafers. To complete the thermal test, the Thermal Demonstration Vehicles (TDVs) were fabricated by bonding the sample onto a customized PDMS holder for fluid connections with the flow loop. A programmable power source was used to heat the TDV in a stepwise manner, and a syringe pump was used to supply the liquid to cool the heat sink. Results show that the heat sink can dissipate heat flux greater than 150W/cm2with substrate temperature lower than 100°C.

The thermal management of a super high heat flux hot spot is critical for the utilization of the new generation semiconductor materials. Among these approaches, the embedded cooling technology has been demonstrated as an efficient way to cool the high heat flux devices. In this work, a silicon base microchannel heat sink was designed and fabricated to cool the hot spots from 50 um to 5000 um. Hotspots were set right above the inlet of the microchannel heat sink and the cooling performance of them were tested via a thermal test vehicle (TTV). The experimental results showed that our thermal management system could dissipate a heat flux of up to 20 kW/$cm^{2}$ in the hotspot of 50 $\mu m\times 50 \mu$ m while temperature rise of the heated area maintained below 270°C.

In this paper, we design and fabricate a radio frequency (RF) signal transmission structure for a 3D stacked structure. Usually, this structure uses co-planar waveguide (CPW) and Through Silicon Via (TSV) to realize the horizontal and vertical RF signal transmission on the same interposer respectively. With the help of micro-bump, we can transport RF signal in a stacked structure. Furtherly, we design and fabricate a patch antenna with a stacked structure, fed by the structure we proposed. Through the measurement of the antenna, we determine the effectiveness of this transmission structure.

In recent years, radio frequency (RF) systems have been moving towards miniaturization. Traditional wire-bonding technology used in RF systems have significant disadvantages in terms of parametric inductance and package size scaling-down. Therefore, people pay more attention to the high-performance and small-size interconnection schemes of RF systems. In this regard, we designed a series of micro bumps arrays for RF application, including arrays with diameters of 15 μm / 30 μm / 40 μm and a pitch of 30 μm / 60 μm / 80 μm. To study RF property of micro bumps array, Cu / Sn micro bumps arrays jointed double-layer coplanar waveguide (CPW) structures were prepared and tested. By subtracting the insertion loss of CPW line from the test structure's insertion loss, the insertion loss of the micro bumps array can be obtained. Comparing the insertion loss of micro bumps arrays with different diameters, the insertion loss of the micro-bumps array with a diameter of 15 μm is the smallest, and the micro bumps with multiple rows have lower insertion loss than a single micro bump. Among them, the insertion loss of a 3 × 6 micro bumps array with a diameter of 15 μm after bonding is 0.15 dB@40GHz.

In this study, we present a Q-band patch antenna with an underling cavity integrated on the stacked high-resistivity Si interposers. A process is developed and sample is fabricated. Evaluation is done and the measurement results shows that it has an operating frequency of 32.75GHz, a -10dB bandwidth of 1.04GHz, a maximum gain of 3dB. Those results prove the feasibility of integrating high-frequency antennas with TSV interposer preliminary.