To address the thermal management challenges of high heat flux, non-uniform temperature distribution, and multiple local hotspots in silicon carbide insulated gate bipolar transistor (SiC IGBT) modules under a dualbridge-arm alternating operation mode, this study proposes a novel double-sided liquid-cooled thermal management scheme dedicated to this type of packaged module. Microchannel heat sinks (MCHSs) are integrated on both module surfaces, and six types of flow-guiding microstructured fins are specifically designed according to the heat source distribution and hotspot regions. Numerical simulations are performed using ANSYS FLUENT to systematically analyze the flow characteristics, temperature distribution, overall thermal performance, and internal stress distribution of the proposed system. Results indicate that microstructure-integrated MCHSs achieve a 38%-51% improvement in overall thermal performance relative to the straight-channel MCHS, without significant pressure drop penalty. Among the designs, the seagull-shaped channel MCHS provides the optimal overall cooling performance for the IGBT module, reducing the average temperature by 3.84 degrees C, achieving an overall thermal performance factor of 1.51, and lowering the maximum stress by 23%. In contrast, the staggered channel MCHS is better aligned with the heat dissipation requirements of SiC power chips, reducing the average chip temperature by 5.16 degrees C, achieving a single-chip temperature difference of only 15.6 degrees C, and reducing the maximum stress by 18%. Tailored flow-guiding microstructures enhance heat dissipation by optimizing flow uniformity and extending the flow paths, and reduce stress concentration induced by coefficient of thermal expansion mismatch by improving temperature uniformity, providing a targeted solution for multi-heat-source IGBT modules.

The microstructure is an important key factor for the reliability of deep through silicon via (TSV) electroplated copper. In the present study, the influence of current density on the surface physical field and microstructure in the electroplated copper were discussed using a combined method of numerical simulation and experiment. The results showed that the optimal electroplated parameters with the defect-free filling were confirmed to be at 0.1-0.17 Ampere per Square Decimeter (ASD) with an accelerator-to-suppressor ratio of 1:10 when the size of deep TSV was Phi 20 mu m & times; 200 mu m with an aspect ratio of 10:1. The microstructure of TSVs exhibited a distinct distribution feature: fine grains along sidewalls and at the mouth, large columnar grains in mid-regions, and equiaxed grains at the bottom. The grain size and the quantity of Sigma 3 twin boundaries first decreased and then increased with increasing current density due to the competing effect of nucleation rate and grain growth by governing the polarization and suppressor desorption. Moreover, the intermediate 9R structure between the matrix and the twin was first observed in the electroplated copper, which provided a new way for strain accommodation in deep TSV electroplated copper, and the matrix-*9R-*twin pathway was proposed through the slip of Shockley partial dislocations. These findings served as a valuable reference for modeling microstructure evolution and laid a foundation for both microstructure prediction and control in deep TSV electroplated copper.

This study investigates Cu-Cu bonding enhancement through various intermediate metal layers (X = Al, Ni, Au, Ti, and Zr) through molecular dynamics simulations. The introduction of intermediate metal layer significantly enhances interfacial atomic migration. Through atom migration and mean square displacement analysis, comprising Cu(100)-X-Cu(100) heterostructures, reveal that Zr demonstrates the most pronounced facilitation of Cu atom diffusion at 400 K, 600 K, and 800 K, exceeding that of Ti at 800 K. This performance correlates with Zr's higher melting point (2125 K) and larger atomic radius (1.60 & Aring;), which facilitate the diffusion of Cu. Ti metal also exhibits strong interfacial reactivity at 400 K, while Au and Ni require temperatures above 600 K for activation. Al intermediate metal layer shows minimal Cu migration due to mismatched atomic radii and higher interfacial energy. These findings establish Zr as the most effective intermediate layer for low-temperature Cu-Cu bonding in 3D integrated circuits.

In addressing the critical thermal management challenges posed by multi-cores and escalating power density in chiplet microsystems, this study undertakes the construction of a series of models for the interlayer microchannel structure within the 2.5D package of the chiplet microsystem. These models are devised to conduct numerical analyses of flow and heat transfer characteristics within the microchannels. Across a R number spectrum spanning from 400 to 1200, the study systematically explores the comprehensive impacts of rib filling modes and arrangements across four distinct configurations, elucidating the underlying mechanisms therein. Moreover, employing the entropy generation rate enables a thorough examination of the irreversibility associated with flow and heat transfer processes. Subsequently, the performance evaluation criterion (PEC) and the field synergy principle Fc are harnessed to compare the efficacy of various microchannel configurations. Notably, amidst the configurations under investigation, the microchannel incompletely filled with aligned ribs (MIFAR) demonstrates superior PEC performance when R numbers exceed 600. However, results derived from the field synergy principle diverge from these findings, attributable to disparities in the weighting of heat transfer capacity and flow resistance between the two criteria. These insights lay a foundation for further optimization efforts aimed at enhancing the performance and cost-effectiveness of microchannels.

In this paper, the fracture toughness and interface reliability of the adhesive film in PoP module are taken as the core, and the bonding strength of the film under shear loading mode is studied by combining experiment and reverse extration method. Firstly, the load-displacement (P-d) curve can be obtained directly through the end notched flexure (ENF) test. Then, the critical shearing fracture toughness GIIC of the adhesive film in PoP module is obtained by extraction from those experimental tests. The 2D finite element model of ENF sample with three-point bending was established. A reverse analysis method is presented to compute and determine the specific cohesive zone law. Finally, the cohesive zone model of the adhesive film are obtained. The average mode II fracture toughness of the adhesive film is 0.268N/mm.

In the back-end-of-line (BEOL) stage of wafer fabrication, the Damascene process is widely used for interconnect metallization, with plasma-enhanced chemical vapor deposition (PECVD), photolithographic patterning, and copper electroplating as the primary steps. The mismatch in the coefficients of thermal expansion (CTE) between the dielectric materials and the silicon substrate results in inevitable wafer warpage during the high-temperature PECVD process. As the number of Damascene interconnect layers increases, warpage accumulates and intensifies, ultimately compromising process stability and wafer yield. This study investigates wafer warpage induced by high-temperature PECVD in the Damascene process using a finite element simulation approach. To capture the cross-scale structural features and real process conditions of wafers more accurately, a representative volume element (RVE) model is introduced, along with the element birth-and-death technique, to enhance prediction accuracy. A predictive model for wafer warpage was developed and validated experimentally, with a simulation error of less than 11.1%. The accurate warpage prediction model provides valuable insights for process optimization, reducing experimental iterations and improving manufacturing efficiency. Additionally, a warpage mitigation strategy is introduced by pre-patterning trenches on the wafer before the Damascene process, facilitating stress redistribution. Simulation results show that this approach reduces wafer warpage by 12.7%, resulting in a significant improvement in wafer planarity.

GaN-on-diamond power devices exhibit superior thermal performance due to the exceptional thermal conductivity of diamond. Enhancing GaN film quality on diamond involves first depositing an AlN seed layer on (111) single-crystal diamond (SCD) substrates via magnetron sputtering, followed by AlxGa1-xN buffer layer growth. However, the influence of polycrystalline AlN (Poly-AlN) layers on the atomic-scale crystalline quality of AlxGa1xN remains underexplored. This study employs molecular dynamics (MD) simulations to investigate the deposition of AlxGa1-xN on Poly-AlN seed layers with varying grain sizes and AlN mole fraction. Results indicate that larger grain sizes reduce grain boundaries, enhancing the crystalline quality of the buffer layer. Additionally, a lower AlN mole fraction increases the lattice constant of AlxGa1-xN, thereby increasing the lattice mismatch with AlN. Post-annealing simulations reveal a reduction in mean biaxial stress by over 50 % and a decrease in average normal stress in the Z direction by more than 35 % in the final equilibrium state.

The development of chip manufacturing and advanced packaging technologies has significantly changed redistribution layers (RDLs), leading to shrinking line width/spacing, increasing the number of build-up layers and package size, and introducing organic materials such as polyimide (PI) for dielectrics. The fineness and complexity of structures, combined with the temperature-dependent and viscoelastic properties of organic materials, make it increasingly difficult to predict the thermo-mechanical behavior of wafer-level Cu-PI RDL structures, posing a severe challenge in warpage prediction. This study models and simulates the thermo-mechanical response during the manufacturing process of Cu-PI RDL at the wafer level. A cross-scale wafer-level equivalent model was constructed using a two-level partitioning method, while the PI material properties were extracted via inverse fitting based on thermal warpage measurements. The warpage prediction results were compared against experimental data using the maximum warpage as the indicator to validate the extracted PI properties, yielding errors under less than 10% at typical process temperatures. The contribution of RDL build-up, wafer backgrinding, chemical mechanical polishing (CMP), and through-silicon via (TSV)/through-glass via (TGV) interposers to the warpage was also analyzed through simulation, providing insight for process risk evaluation. Finally, an artificial neural network was developed to correlate the copper ratios of four RDLs with the wafer warpages for a specific process scenario, demonstrating the potential for wafer-level warpage control through copper ratio regulation in RDLs.

Effect of flip chip bonding parameters on microstructure at the interconnect interface and shear properties of 64.8Sn35.2Pb microbumps were investigated in this work. Results show that the main intermetallic compound (IMC) at the interconnect interface is (Ni, Cu)3Sn4 phase, and meanwhile a small amount of (Cu, Ni)6Sn5 phase with a size of 50–100 nm is formed around (Ni, Cu)3Sn4 phase. The orientation relationship of [ 156 ](Ni, Cu)3Sn4//[152](Cu, Ni)6Sn5 and (601)(Ni, Cu)3Sn4//( 201 )(Cu, Ni)6Sn5 is found between these two phases, and the atomic matching at the interface of the two phases is low. The highest shear force of 77.3 gf is achieved in the 64.8Sn35.2Pb microbump at the peak temperature of 250 °C and parameter V1 because dense IMCs and no cracks form at the interconnect interface. Two typical fracture modes of microbumps are determined as solder fracture and mixed fracture. The high thermal stress presenting in the thick IMCs layer induces crack initiation, and cracks propagate along the α/β phase boundaries in the Sn-Pb solder under shear force, leading to a mixed fracture mode in the microbumps.

Through analyzing different cross-sections of the complex ball grid array (CBGA) sandwiched by silicon interposers, various distributed capacitances of the CBGA and the significance of the CBGA's coplanar capacitances are revealed. From the analyses, the composition of the CBGA's capacitance is found to have similarity with that of the coplanar waveguide's capacitance. Based on the electric-field coupling mechanism of the coplanar waveguide, geometrical analysis of the CBGA, and analysis of multiconductor transmission lines, analytical equations are derived to allow accurate modeling the equivalent circuit of the CBGA for 3D silicon-interposer packaging. The modeled equivalent circuit of the CBGA is validated with the full wave electromagnetic simulation, and it is demonstrated to have a good accuracy up to 40 GHz. Moreover, the CBGA structure can be further optimized for impedance matching with the guidance of the derived analytical equations.

This paper proposes an ultrathin high-frequency selective frequency selective surface (FSS), which is composed of three metal layers and two dielectric substrates. The receiving patch and transmitting patches are integrated separately on the top and bottom GND layers, respectively. A stripline central guide structure is etched on the middle GND layer. To improve frequency selectivity, a quarter-wavelength stripline resonator is added. High frequency selectivity is also maintained when electromagnetic waves with oblique incidence angles within 40° are incident on the proposed third-order FSS. The frequency selectivity of the proposed third-order FSS at the left and right edges of the passband is 371 dB/GHz and 386 dB/GHz, respectively. It is indicated that the proposed third-order FSS has high frequency selectivity and wide application in the field of electromagnetic compatibility

In this paper, the capacitance characteristics of the TSV structure are analysed from the viewpoint of electromagnetic simulation and circuit simulation. It is concluded that the method of superposing and summing the capacitance of each decomposed structure is not applicable to this structure. On this basis, a method to obtain an equivalent circuit model (ECM) of the TSV structure is proposed based on de-embedding - the LC virtual separation method. The model is validated by testing in the frequency range of 0-40 GHz.

Evolution mechanism of interfacial multi-layer intermetallic compounds (IMCs) and their impact on failure behavior in Al-Au wire bonding after thermal storage and thermal cycle process are investigated. Microstructural analysis shows that multi-layer IMCs form between the Al wire and barrier layer. After thermal storage and thermal cycle process, the Au8Al3 layer transforms into AuAl2, and Au pad transforms to a thicker layer containing Au2Al and AuAl. Thermodynamic analysis indicates that Au8Al3, Au2Al, AuAl, and AuAl2 have increasing stability. Small-size, equiaxed AuAl2 grains form due to high stored energy, while large-size, columnar Au2Al and AuAl grains result from slower reaction rate and limited recrystallization. The stack-like formation of AuAl2 grains is attributed to the balance between driving force and interfacial energy resistance. During thermal storage, thicker IMC layers cause cracking between IMC layers and Au pad, and micro voids form near the IMC layers/barrier layer interface due to Kirkendall effect. Thermal stress results show that plastic deformation of the Al layer slightly affects the thermal stress in other layers during the thermal cycle process. The cyclic stress at the interface with initial cracks ranges from -157 MPa to 114 MPa, facilitating crack propagation. Additionally, micro void grows under cyclic thermal input, weakening interface adhesion. Therefore, bond strength decreases and frequency of bonding lift-off with cracking along the IMC layers/barrier layer interface increases after thermal storage and thermal cycle process. These results provide the guidance for regulating the interfacial IMCs and predicting the thermal stress in Al-Au wire bonding.

The ternary system of BaTiO3 (BT)-based lead-free ceramics ((1-x)BaTiO3-x(0.94 Sr0.7Bi0.2TiO3- 0.06BiMg0.5Ti0.5O3) are investigated on their structural, dielectric and ferroelectric properties. The struc-tural evolution is identified from the tetragonal phase (P4mm) to the pseudocubic phase with increasing the dopant concentration x. The gradually diffusive dielectric peak and highly dispersive relaxor behaviors are recognized, indicating the transformation from ferroelectric to relaxor state. Meanwhile, the ceramics are characterized by the slim polarization hysteresis loops associated with polar nano-sized cluster formation. Complex impedance spectroscopy reveals the electrical inhomogeneities with enhanced boundary effect caused by the excessive addition, leading to the abnormally degraded electric breakdown strength. Combined with the X-ray photoelectron spectroscopy, the oxygen vacancy hopping mechanism is proposed for the high dopant concentration, contributing to the diffuse dielectric response. As a result, optimized energy-storage density and efficiency are simultaneously obtained at a relatively low electric field. All these features demonstrate an effective route in the composition modulation of BT-based dielectric capacitor ceramics that not only the formation of polar nano regions but also the electrical homogeneities can greatly influence the comprehensive dielectric performance.(c) 2022 Elsevier B.V. All rights reserved.

The decreasing-width, increasing-aspect-ratio RDL presents significant challenges to the design for reliability (DFR) of an advanced package. Therefore, this paper proposes an ML-based RDL modeling and simulation method. In the method, RDL was divided into blocks and subdivided into pixels of metal percentage, and the RDL was digitalized as tensors. Then, an ANN-based surrogate model was built and trained using a subset of tensors to predict the equivalent material properties of each block. Lastly, all blocks were transformed into elements for simulations. For validation, line bending simulations were conducted on an RDL, with the reaction force as an accuracy indicator. The results show that neglecting layout impact caused critical errors as the substrate thinned. According to the method, the reaction force error was 2.81% and the layout impact could be accurately considered with 200 × 200 elements. For application, the TCT maximum temperature state simulation was conducted on a CPU chip. The simulation indicated that for an advanced package, the maximum stress was more likely to occur in RDL rather than in bumps; both RDL and bumps were critically impacted by layouts, and RDL stress was also impacted by vias/bumps. The proposed method precisely concerned layout impacts with few resources, presenting an opportunity for efficient improvement.

随着集成电路制程趋于极限,登纳德缩放定律逐步失效,芯片的功率密度逐渐提升,尤其是在5G、物联网以及高性能计算快速发展的驱动下,单芯片面积也在增大,热耗散问题日趋严重,传统的冷却方式已无法保证芯片的可靠工作.将热沉制备在芯片内部可以避免封装材料的导热热阻和多层界面热阻,提升冷却性能和冷却效率.学术界针对芯片的嵌入式微流体冷却开展了大量卓有成效的研究和探索,不断提出新型通道结构设计方案,包括平行长直通道、歧管通道、射流通道等.旨在于优化泵功和热阻,在小压降下实现高效冷却.然而,随着芯片面积的增大,在限域空间实现高效冷却将更加困难,工艺难度和制造成本限制了嵌入式液冷的大规模商业化使用,目前在实际IC芯片内演示的冷却方案验证了嵌入式冷却的性能,但复杂度高,兼容性差,冷却性能有待进一步提升.尤其是在3D封装架构下,需要提出兼容小型化、高密度封装的通道结构,通过协同设计,在保证电学互连的前提下实现层间冷却.在优化通道结构设计的同时,还需要简化工艺,降低成本,提升嵌入式微流体冷却的工艺可靠性和长期工作可靠性,才能推进嵌入式微流体冷却技术的实际应用.

Advanced packaging technology based on TSV interposer becomes more and more important in microsystem integration. Electrical performance is one of the primary concerns in microsystem packaging design. The electrical characteristics of materials and process variation determine the voltage drop and transmission of high-speed and high-frequency signal. In this paper, simulation and test fitting of scattering parameter (S-parameter) and multi-objective comprehensive optimization method is proposed to characterize polyimide (PI) used in the TSV interposer. According to the original dielectric constant (Dk) and dissipation factor (Df) of PI, embedded single-ended microstrips are designed through simulation to obtain low reflection transmission and fabricated. In our method, Dk and Df of PI and conductivity of copper are set as variables to be optimized. Djordjevic-Sarkar model is adopted for frequency-dependent performance of Dk and Df. The simulation and measurement results including magnitude and phase of insertion loss, return loss and direct-current (DC) resistance are fitted well to extract the material characteristic curves. As a result, frequency-dependent curves of Dk and Df from 10MHz to 40GHz and the conductivity of copper are given. In additional, the influence of surface roughness has been integrated in Df and conductivity, which is more suitable and convenient for the engineering application.

High-speed digital microsystems has emerged as one of the most important solutions for improving system performance, bandwidth, and power consumption. Based on mature micro-system processing technology, a material extraction approach for silicon interposer applied for high-speed digital microsystems was presented in order to obtain frequency-dependent precise material parameters. By combining microwave theory and mathematical model of iterative algorithm, the dielectric constant (Dk) and the dissipation factor (Df) of polyimide dielectric layer is acquired, which minimizes testing costs and streamlines testing process. The method is based on two-port transmission/reflection measurements. Vector Network Analyzer (VNA) is used to extract the scattering parameters with an extraction range of 1 MHz to 10 GHz. The algorithm is programmed using MATLAB. The observed Dk values at 2 GHz, 6 GHz, 8 GHz, and 10 GHz are, respectively, 3.22, 3.04, 2.96, 3.03, and 2.91, while the corresponding Df values are 0.021, 0.025, 0.026, 0.026, and 0.024. Finally, the complex permittivity derived is simulated and analyzed using Ansys HFSS. The results verify the validity of the theoretical method and proves that the values of the complex permittivity obtained by the method in this paper are reliable.

为推进航天电子微系统技术自主可控,并达到国际领先水平,本文以微系统技术的发展需求为基点,从总体路线和技术路线两个角度论述,在"微系统协同设计技术"、"微系统制造技术"、"微系统产品规划"三个方面为微系统的发展提出可行性和战略性的建议,进一步支撑中国航天事业实现高质量、高效率及高效益的发展.

研究依托硅通孔实现信息处理微系统的技术.概述了传统信息处理系统小型化集成实现方式及新需求下所面临的发展瓶颈,依托"拓展摩尔定律"(More than Moore)战略成为信息处理系统具备高密度、多功能、多工作模式能力的重要实现方式,硅通孔TSV(Through Silicon Vias)为上述需求提供了重要的支撑手段;着重阐述了信息处理类微系统的优势和设计、实现、测试等方面的关键技术,并展示了已实现的多种信息处理微系统产品组成形态,最后对信息处理微系统产品的应用前景进行了展望,阐述了关键技术对信息处理微系统实现支撑的优越性.