To enable accurate system-level electrostatic discharge (ESD) simulation, this article applies statistical learning to obtain I/O port models of the victim integrated circuits (ICs). A quasi-static I–V model derived using kernel regression can capture the circuit board dependency of the behavior observed at the I/O pin, regardless if there is snapback. The non-parametric kernel model can be reduced to a system-specific parametric model, which has smaller requirements for computing time and memory. In some cases, transient system-level ESD simulation may require the IC model to replicate the dynamic behavior of the nonlinear circuit. A recurrent neural network is demonstrated to be a suitable model in such cases. This article provides a detailed RNN training flow for IC pin modeling, and presents a Verilog-A implementation of the RNN for use with Simulation Program with Integrated Circuit Emphasis (SPICE)-type simulators.

The widespread availability of high-quality open source software for behavioral model optimization motivates the investigation of a behavioral approach to the modeling of aged circuits. A continuous-time formulation of a recurrent neural network (RNN) is compatible with transient circuit simulation, and this work evaluates RNN applicability to the modeling of aged circuits. For any reasonable input, the model should be required to produce an output response that is physically plausible. Approaches to imposing physical constraints on black-box models are outlined briefly.

To enable accurate system-level ESD simulation, the quasi-static I-V model of an IC is enhanced through kernel regression to reflect its circuit board dependency; alternatively, a recurrent neural network may be used to generate a non-quasi-static transient model. Hybrid electromagnetic and circuit simulation is demonstrated for ESD-induced noise coupling analysis.

This paper presents a method for data-driven behavioral modeling of electronic circuits using recurrent neural networks (RNNs). The RNN structure is adapted based on known characteristics of the system being modeled. The discrete-time RNN is transformed to a continuous-time model and then implemented in Verilog-A for compatibility with general-purpose circuit simulators.

The pulse width dependency of the failure current for NPN structures in a 0.18-μm BiCMOS technology is studied using measurements and TCAD simulation. The desired “Wunsch-Bell” behavior is not observed due to formation of current filaments in this device; however, the failure current for long pulse widths can be increased by layout changes.

This work presents a model for multi-finger MOSFETs operating under ESD conditions. It is a distributed model that can reproduce the effect of layout geometry on trigger voltage, on-state resistance, and non-uniform turn-on of device fingers. A three-terminal transmission line pulsing technique enables model parameter extraction. Analysis of measurement data and TCAD simulation reveals that self-heating is not uniform across the device, and this affects the relation between on-state resistance and the number of fingers. With self-heating incorporated, the model correctly reproduces the device I–V curve up to high current levels.

A new layout of the GGSCR ESD protection device is proposed for transient voltage overshoot reduction. The superior performance of the modified layout is verified in 65nm CMOS technology. Even with the modified layout, key layout spacings, such as the well-tap spacing and the anode to cathode spacing, affect the overshoot voltage. An n-well triggered version of the GGSCR is compared with the usual p-well triggered device and is shown to have larger overshoot. Finally, the susceptibility of the trigger GGNMOS to undergo early failure is investigated.