The vulnerability of parasitic SCR, integrated with laterally diffused MOS (LDMOS) device (conventional LDMOS-SCR), to trigger during MOS/switching operation was addressed using an engineered (Flipped) LDMOS-SCR configuration, which in turn resulted in a unique low current/window electrostatic discharge (ESD) failure. While the failure was found to be universal to LDMOS-SCR devices with a weaker parasitic SCR, designed as an efficient MOS switch, it was found to be specific to a window of current between trigger and holding state. Besides, it couldn't be detected using a standard 50- Omega loadline transmission line pulse (TLP). The window failure resulted in severe power-to-fail scalability issues in LDMOS-SCRs, which were noticed in system-level stress, high impedance TLP, and long pulse stress. In this work, while using systematic experiments performed by a high-resistance load-line TLP and 3-D technology computer-aided design (TCAD) simulations, we have developed detailed physical insights into the low current or window ESD failure phenomenon in these LDMOS-SCR devices. Physical insights developed in this work have resulted in device design proposals to avoid such failures and mitigate power-to-fail scalability issues during ESD stress while keeping the MOS operation and performance intact.

A new SCR-LDMOS is investigated through 2D/3D TCAD simulations to obtain maximum holding voltage, minimum area and high ESD robustness. The effect of the additional floating-p region is studied. Reduced overvoltage and turn-on time are observed in the very-fast pulsed regime. Tunability of holding voltage is demonstrated.

A conventional silicon-controlled rectifier integrated into a laterally diffused MOSFET (SCR-LDMOS) is studied through 2D TCAD simulations in order to obtain the maximum holding voltage without increasing the area consumption or degrading the power-to-failure robustness. A reference device with 150V trigger voltage, 3V holding voltage and an approximate thermal breakdown at 30 mA/mu m is adopted. Different configurations of the drain-side region are compared, with the best solution showing a 5x improvement on the holding condition without a significant variation on the other figures of merit.

This article presents a 2-D analytical model for the potential and current characteristics of thin-film transistors (TFTs) using Green's function approach. The model accurately incorporates the effects of nonuniform trap charge distribution in the channel and includes both top and bottom gate oxide regions with different thicknesses. Solving 2-D Poisson's equation, we derive closed-form 2-D expressions for the potential profile in the channel. While the model applies to any thin-film technologies such as indium oxide (In2O3), indium gallium zinc oxide (IGZO), graphene, carbon nanotubes (CNTs), etc., in this work, the model is validated using experimental data and TCAD Sentaurus simulations for In2O3 TFTs. Key results include analysis of short-channel effects (SCEs), gate oxide scaling, and channel thickness variations on device performance. The model successfully predicts subthreshold characteristics and drain-induced barrier-lowering (DIBL) while identifying the limitations in the ON current region due to the absence of various scattering phenomena, such as surface scattering in the analytical formulation. An improved mobility model, accounting for field dependence, enhances the accuracy in the ON region, ensuring agreement with experimental and TCAD data across various bias conditions.

Physical insights into the impact of the thin-oxide polysilicon gate on the on-resistance of DeMOS-based HV-PNP are developed using detailed TCAD simulation. Turn-on and eventual failure mechanisms in HV-PNP are discussed. The impact of thin-oxide polysilicon placed over the N-Well and P-Well regions is investigated separately. The physics of regenerative bipolar degradation and its effect of dynamic onresistance is understood as a function of thin-oxide placement. Furthermore, floating the thin-oxide gate mitigated regenerative bipolar degradation while having a faster lateral PNP trigger, resulting in the best case of on-resistance at all current levels. The insights developed in this work help to design compact high-voltage PNPs.

This paper investigates a method to increase the holding voltage in a conventional Silicon Controlled Rectifier (SCR) for ESD power clamping. Specifically, a SCR-LDMOS device with 150 V trigger voltage and 9 V holding voltage is investigated assuming the application of high-energy electron irradiation. Based on previous experimental and TCAD investigations, the most relevant kind of defects is accounted for at different irradiation levels clearly showing an increase of the holding voltage up to 16 V without any other significant change in the TLP characteristics. The role of trapped charges in the holding regime has been addressed up to the thermal runaway through extensive numerical investigations.

The root causes for the anomalous Pf-tf scaling behavior in the adiabatic regime are identified for a BiCMOS-based ESD protection for the first time. TCAD is used both to understand the turn-on of the integrated architecture with two coupled bipolar transistors under different ESD pulses and to explore the main physical mechanisms leading to the thermal runaway and failure. Simulations clearly show the complex interaction between the conductance modulation and the onset of hot spots in the full volume of the device structure, leading to the identification of critical parameters for the optimization of the proposed ESD cell.

This article discloses a unique failure mode in high-voltage bidirectional (Bi-Di) silicon-controlled rectifier (BDSCR) cells during International Electrotechnical Commission (IEC) air discharge electrostatic discharge (ESD) events. Failure was found to be sensitive to IEC measurement conditions or variabilities such as the speed of IEC gun and angle of approach, which causes different stress rise times. Hence, observed failure was a peculiar function of the rise times of the discharge current waveform. Remarkably, failure in high-voltage BDSCR was observed only for a window of current rise times. A new approach is presented using 3-D TCAD simulations of multifinger BDSCR to study and probe the failure mechanism dependent on these system-level stress parameters and variabilities. By emulating the experimental conditions in a 3-D TCAD environment, physical insights are developed to probe the root cause of the observed air discharge failures. Furthermore, a device engineering approach has been proposed, with the help of 3-D TCAD simulations of multifinger BDSCR, which computationally demonstrated improved robustness of BDSCR multifinger cells against IEC air discharge failures. The proposed design mitigates the nonuniform turn-on and failure due to IEC stress or rise time variability at the cost of a negligibly small area overhead.

The concept of abutting source/body and drain/anode junctions is studied in detail in a high voltage LDMOS-SCR with 2D and 3D TCAD simulations. The SCR turn-on and low current filament formation are strongly influenced by the isolation at the anode and cathode side in the LDMOS-SCR. While the anode side isolation impacts the filament-induced failures at low currents, the cathode side isolation has a minor impact. Physical insights are given on the SCR turn-on degradation with abutting and its influence on the filament formation and spreading. The obtained understanding helps to build an ESD robust, self-protected LDMOS-SCRs.

In this article, a novel design approach for improving electrostatic discharge (ESD) robustness of high-voltage laterally double-diffused MOS (LDMOS) devices is presented using detailed 3-D TCAD simulations. The proposed method considers engineering both static filament and dynamic/moving current filaments in LDMOS design. Physical insights and engineering approaches for moving filaments at higher stress current levels are presented. Dynamic filament motion and its relation to n-p-n turn-on engineering with an optimum p-well profile and substrate biasing are revealed. A unique window failure in LDMOS near snapback is discussed for the first time. A detailed analysis is presented on filament width engineering by using optimum drain diffusion length (DL) and its influence on static filament-induced window failures. This approach resulted in ten-time improvement in ESD robustness for self-protecting concepts. Finally, different fundamental questions related to the origin of filament motion are explored (using 3-D TCAD) with the help of engineered LDMOS Designs.

A unique failure mechanism for International Electrotechnical Commission (IEC) stress through a common-mode (CM) choke is investigated. The presence of a CM choke in the stress path was found to change the current waveform shape that the electrostatic discharge (ESD) protection device experiences on-chip. Minor variations in the stress current waveform shape for specific IEC stress levels are found to cause an unexpected window failure in drain-extended nMOS silicon controlled rectifier (DeNMOS-SCR). The 3-D technology computer-aided (TCAD) simulations are used to understand the device behavior and failure under the peculiar two-pulse-shaped IEC current waveform attributed to the presence of a CM choke. DeNMOS-SCR failure sensitivity to different components of the unique pulse shape is studied in detail. A novel device architecture is proposed to increase the DeNMOS-SCR robustness against the peculiar two pulse stimuli. The proposed DeNMOS-SCR was found to eliminate the window failures against system-level IEC stress through a CM choke in communication pins in automotive ICs. The proposed concept is universal and can be extended to all high-voltage DeNMOS-SCRs. A detailed physical insight is provided for the operation of the engineered structure.

Lateral parasitic PNP transistor inside P+/N-well diode is explored and investigated for the electrostatic discharge (ESD) protections in I/O interface integrated circuits (ICs). An analysis for the breakdown behavior of the lateral parasitic PNP transistor with base floating is presented for the first time. Simulations on the lateral parasitic PNP transistor have been performed to understand the effects of geometry parameters on current gain beta, triggering voltage Vt1 and on-resistance RON. The test structures were fabricated using the UMC 65 nm low-k logic/mixed-mode CMOS process and characterized with the transmission line pulse (TLP) system. The TLP characterization results demonstrate that the triggering voltage Vt1 is strongly influenced by the base region (i.e., base width), and on-resistance RON is mainly affected by the collector region (i.e., collector width) for the fingertype parasitic PNP. Meanwhile, the scalability of thermal failure current It2 has been studied in terms of the periphery of the lateral parasitic PNP and the whole device width.

New design approach for improving ESD robustness of High voltage LDMOS devices is presented using detailed 3D TCAD simulations by developing physical insights and engineering approaches for moving filaments. (i) NPN turn -on engineering by using an optimum P-well profile & substrate biasing and (ii) filament width engineering by using optimum drain diffusion length (DL), shows how static filament can be modified to achieve dynamic (moving) nature. This approach resulted in 10× improvement in ESD robustness for self-protecting concepts.

Power-scalability issues for longer pulse duration discharges (PW>100ns) in high voltage LDMOS-SCR devices is evaluated. The severity of the problem with increasing LDMOS voltage classes is highlighted with a need for newer design strategies. A systematic design approach is presented to evaluate the effect of different design parameters on LDMOS filament and SCR turn-on near the snapback region. Finally design guidelines are presented to improve the power scalability without compromising on its ON-state DC (functional) and Safe Operating Area (SOA) characteristics.

Case study on HBM ESD protection using gate-coupled SCR is presented. The failure mechanism of DENMOS devices due to the voltage overshooting of SCR is discussed. It is demonstrated that effective HBM protection cannot be estimated by only comparing the TLP triggering voltage of gate-coupled SCR and internal circuitry. Additional protection scheme need to be implemented to provide sufficient HBM ESD protection.

A unique low current ESD failure during snapback region, which otherwise survive high current stress, is reported in LDMOS-SCR device. The failure is universal to LDMOS-SCR devices designed as self-protected MOS switch and found to be specific to a window of current between trigger and holding state, which can only be captured using high resistance load-line in TLP system. This resulted in severe power scalability issues in LDMOS-SCRs. In this work, while using systematic experiments and 3D TCAD simulations, we have developed detailed physical insights into the unique low current ESD failure phenomenon in LDMOS-SCR devices.

Physical Insights into the early formation of current filaments in High Voltage SCR is presented. Repeated current filamentation and subsequent filament spreading, which in turn results in filament motion, is detected using 3D TCAD. Impact of different load lines on ESD robustness and filament dynamics with ESD stress duration has been studied using experiments and 3D TCAD simulations. Finally, impact of silicide blocking in mitigating filament strength has been studied, which in turn improves the ESD robustness.

In this work we address turn-on vulnerability of conventional LDMOS-SCR devices under standard circuit operation window. This behavior is correlated with early ESD / SoA failure and power-to-fail scalability issue in HV LDMOS-SCR devices. The 3D TCAD is used to Develop physical insights into the performance and reliability limiters of LDMOS-SCR device. Different engineered designs are proposed to mitigate turn-on vulnerability and ESD power to fail scalability, while keeping channel performance and hot carrier degradation unaffected.

Technology advances continue to pose significant challenges to electrostatic discharge (ESD) design, despite ESD being a mature and overall understood topic.