Adaptive clocking becomes more popular and it is very effective to mitigate low and middle frequency power noise impact on timing or fmax of micro-processor designs. In the meantime, clock-data jitter tracking can effectively address high frequency noises. This paper is to consider these two effects and examine power noise sensitivity in the full bandwidth of noises.

RC termination for sideband signals is required in PCIe Gen4 Card Electromechanical specification to reduce crosstalk in PCIe connectors. A new approach to reduce crosstalk is proposed in this paper. This approach doesn't require extra components, and simulation results show that the new proposal can achieve even better electrical performance.

A modeling method to consider simulation switching noise of HBM and its impact on HBM timing is described. This method combines partial element equivalent circuit model for power delivery network and S-parameters based HBM channel model together in HBM studies.

Power supply noise can significantly degrade circuit performance in modern high-performance SoCs. Adaptive clocking schemes have been proposed recently that can tolerate power supply noise by adjusting the clock frequency in response to fast-changing voltage variations. In this paper, we model and quantify power supply noise tolerance with a fine-grained globally asynchronous locally synchronous (GALS) design style together with an adaptive clocking scheme. An experimental setup that includes SPICE and Verilog-A models is used to quantify the effect of clock-tree insertion delay and spatial workload variations on power supply noise tolerance in both traditional synchronous adaptive clocking and a fine-grained GALS adaptive clocking scheme. Compared to the traditional scheme, fine-grained GALS adaptive clocking significantly reduces these effects and the margins required to tolerate power supply noise. The gain is quantified using the uncompensated voltage noise metric, which is defined as the additional voltage margin that is required for failure-free operation of circuits at the frequency dictated by the adaptive clocking scheme. In our experimental setup for a typical high performance SoC, fine-grained GALS adaptive clocking achieves a 78 mV saving in uncompensated voltage noise, which is an equivalent of 15% savings in power.

Power noise aware clocking in modern chips can reduce power supply noises and relax on-chip timing requirements during power drooping. This paper proposes and demonstrates a power noise simulation method to consider these two effects. Measurement results are also presented.

GPU for high performance computing shows high current consumption and fast current variation which presents a big design challenge for power delivery. In this paper, power delivery design for a computing GPU is discussed focusing on package capacitors. Current behaviour of a computing application is illustrated first. The related power delivery challenge is presented with simulation and measurement. Next package capacitors are proposed to reduce noise and studied via simulation according to their placement, value, number, and type. Simulation data shows land side cap placed between IO rails and core VDD balls can effectively reduce power delivery noise without compromising BGA density. Measurement data correlates well with simulated power noise. There is about a 55mv noise improvement which yields a gain of 150MHz in GPU operational frequency.

Electrical modeling of Through Silicon Vias (TSVs) is very important for three dimensional (3D) system design and analysis. It has attracted much research attention in recent years. Most of the previous research focuses on fitting circuit parameters to the frequency response obtained from measurements or full-wave discretization based electromagnetic simulations. The extension of these methods to multiple TSVs can be challenging because of the significant increase in computational cost. In this paper, we proposed a novel circuit model for multiple TSVs. Since frequent switching of high speed signals can dynamically bias TSV metal insulator semiconductor (MIS) interface and allocate TSV MIS into accumulation or depletion regions, the TSV capacitance is nonlinear and dependent on the biasing of the TSVs. An analytical expression for capacitance is introduced and a new circuit model is proposed accordingly. The circuit model accurately captures all the parasitic elements of various TSVs arrangements and accounts for wide frequency range, high frequency skin effect, eddy currents in substrate, and metal oxide semiconductor (MOS) effect.

Through Silicon Vias (TSVs) constitute key components interconnecting adjacent dies vertically to form three dimensional integrated circuit (3D IC). In this paper, we present an accurate electrical circuit model for differential through silicon vias (TSVs) considering the metal oxide semiconductor capacitance effects and study the effect of differential TSVs on the signal integrity with high data rate signals (up to 25Gbps) using eye diagram approach. Furthermore, we find the nonlinear TSV capacitance has the most predominant impact for the 3D IC performance, and thus, its negative effect to the system performance should be minimized. We optimize the parameters of TSVs architecture and manufacturing process to obtain the minimum depletion capacitance in the desired operating voltage region based on the nature of the TSVs C-V characteristics. Our study shows minimizing the TSVs capacitance could significantly improve the 3D IC performance, which help in developing effective design guidelines for TSVs in 3D IC.

This paper proposes an equivalent lumped element model for the differential Through Silicon Vias (TSVs) with considering the effect of voltage dependent and nonlinear capacitance. The modeling and analysis of the differential signaling with TSVs play a critical role in designing the high performance TSV channel in the three dimensional integrated circuit (3D IC). TSVs have been mostly modeled assuming that the TSV metal insulator semiconductor (MIS) interface is not biased and the silicon substrate is a lossy, low conductive medium. Ignoring the semiconductor properties of the substrate and the resulting MOS capacitance introduce significant inaccuracies in the TSV modeling. In this paper, we investigate the complementary nature of differential signals which introduces a virtual ground and automatically biases the TSV MIS interface, causing carrier accumulation and depletion. Furthermore, the large digital signal swing makes the depletion region change the depletion width dynamically, which introduces a nonlinear and large signal TSV capacitance. The capacitance is modeled analytically and a new equivalent circuit model for the differential TSVs is proposed accordingly. The impact of the voltage dependent and nonlinear capacitance on the performance of high speed differential signals is analyzed through channel simulations with eye diagram approach.

Through Silicon Vias (TSVs) have been mostly modeled assuming that the TSV metal-insulator-semiconductor (MIS) interface is not biased and silicon substrate is just a lossy, low conductive medium. These modeling methods are based on small signal analysis and don't consider semiconductor carrier accumulation or depletion due to static biasing or large signals. This paper argues that the complementary nature of differential signals introduces a virtual ground and that the voltage difference between a TSV and the virtual ground automatically biases TSV MIS interface, causing carrier accumulation or depletion. In the meantime, large digital signal swing makes the depletion region to change its width dynamically, which introduces a non-linear, large signal TSV capacitance. This capacitance is modeled analytically in this paper, a new equivalent circuit model for differential TSVs are proposed, and the impact on the performance of high-speed differential signals is examined in channel simulations.

Minimizing crosstalk is a major concern in high-speed differential buses design. The power/ground pins are distributed uniformly and the performance of a bus is usually gated by the performance of the worst differential signal in the bus. In this paper, we propose a fast algorithm to generate nearly uniform power/ground distributions by applying force-directed optimization. With each power/ground distribution, our linear perturbation algorithm enumerates the differential signal pairing combinations. The algorithm is further sped up significantly by our branch-and-bound scheme and max information gain signal selection. These differential signal assignments are then assessed by applying a benchmark parameter that describes the relative performance of each assignment. Experimental results demonstrate the high efficiency and significant electrical benefit of our algorithm.

This paper discusses electrical performance and design aspects of SAS (Serial Attached SCSI) link channels in various server storage system configurations through modeling and simulation analysis in frequency and time domain. The signal loss behaviors are investigated in two interconnect structures, internal SAS links in host enclosure backplanes and external SAS links in cabling environment. While signals in external SAS links experience excessive loss through lengthy cables in meters, those of internal SAS links are impaired by multiple discontinuities of board components over less than a couple of feet of PCB routing though largely dependent of system design. While eye closure is parallel to loss magnitude in general, higher degree of discontinuities exhibited in frequency loss behavior of channels result in more eye closure despite lower loss magnitude reducing design space budget and the impact is greater with higher data rates.

The continuous increase in microprocessor performance demands an equal order of increase in the bandwidth requirements on the memory and I/O interfaces. Providing the required bandwidth at an acceptable cost is a challenge to the system packaging engineer. This paper discusseshow a passive channel can be optimized in a cost effective way to provide the maximum bandwidth. The paper focuses on the design methodology including modeling the channel, identifying the channel bottle-necks, optimizing around the bottle-necks and verifying the conclusions through simulation. Finally the simulation results are verified through hardware measurements.

Vias in packages and boards, land-grid-array pins, and connector pins introduce significant crosstalk noise in high-speed differential buses. In this paper, we propose an algorithm that minimizes crosstalk noise by optimizing power/ground distribution as well as differential signal assignment. Experimental results demonstrate its high efficiency and significant electrical benefit.