Electromagnetic coupling between ThroughSilicon Vias (TSVs) and adjacent metal wires in 2.5D interposer integrated chips (ICs) is a critical signal integrity (SI) concern for high-speed server systems. While TSV technology offers significant advantages such as shorter interconnect length, reduced power consumption, and faster speed; their close proximity to package metal wires introduces parasitic capacitance which can severely degrade the signal integrity to the point of eye closure. This paper presents numerical analysis and hardware measurement data of the impact of such parasitic coupling in high-speed computer circuits. Frequency as well as time domain results are reported to illustrate the importance of controlling the capacitive coupling between TSVs and routing wires using keepout zone (KOZ) to ensure fast, reliable and robust computing system designs.

Signal integrity (SI) in high-speed channels is becoming more critical by the day with increasing data rate of modern computer server systems. Crosstalk generated within the densely packed via/pin field is one of the major sources of SI performance degradation. This work focuses on the tightly pitched striplines within the pin field region of multi–layer printed circuit boards (PCBs) and studies the far-end crosstalk (FEXT) behavior for two frequently adopted routing approaches– "zigzag" and "arc". Electromagnetic modelling and SI analysis are carried out to analyze and quantify the FEXT effect in the two routing configurations with the inclusion of the PCB misregistration effect. Additionally, crosstalk study on the implementation of "tabbed lines" for the two types of pin area wiring is reported. Based on the observed results, routing guidelines are summarized and discussed for improving FEXT within a via filed.

The via-in-pad plated over (VIPPO) and the dogbone fanout structures for high-density interconnects are modeled and their high frequency performances are compared. Signal integrity (SI) metrics such as impedance matching, signal loss and crosstalk are analyzed. Compared to the traditional dogbone fanout, the VIPPO fanout features broader impedance matching bandwidth and reduced noise coupling length due to the removal of the parasitics from the dogbone. The SI benefits of the VIPPO vs. the dogbone fanouts are verified further with the eye diagram simulation in channel configurations of a back-to-back module-level channel and a 12dB-loss chip-to-chip system channel. It is shown that the VIPPO structure significantly improves the RMS jitter noise (~40% with the modules at 40Gb/s) and the eye openings (~25% at the system level at 32Gb/s).

With increasing bandwidth and higher transmission data rates in each generation, routing density in motherboards especially under module area have also increased proportionally. Maintaining signal integrity of high-speed channels under such dense routing conditions is becoming more challenging in each new product generation. This paper shows how via to trace coupling in under LGA area can give rise to increased NEXT values thereby causing channel margin loss and failure at high data rates.

The POWER10™ processor designed for enterprise workloads contains 16 synchronous SMT8 cores (Fig. 2.4.1) coupled through a bi-directional high-bandwidth race-track [1] [2]. A SMT8 core with its associated cache is called a core chiplet, and a pair of core chiplets forms a 39.4mm2 design tile. Designed in a 7nm bulk technology, the 602mm2 chip (0.85× of POWER9™ [3]) has nearly 18B transistors, 110B vias and 20 miles of on-chip interconnect distributed across 18 layers of metal: 8 narrow-width layers for short range routes, 8 medium-width layers for high performance signals and two 2160nm ultra-thick metal (UTM) layers dedicated for power and global clock distribution. There are 10 input voltages as shown in Fig. 2.4.1: core/cache logic (Vdd), cache arrays (Vcs), nest logic (Vdn), two PHY voltages (Vio, Vpci), stand-by logic (Vsb), a high-precision reference voltage (Vref), DPLL voltage (VDPLL), analog circuitry voltage (VAVDD), and an interface voltage (V3P3). The C4 array contains 24477 total connections (1.25× of [3]) with 10867 power, 11879 ground and 1731 signal connections. A core and its associated L2 cache are power-gated together, while the L3 cache is power-gated independently.

Tightly pitched differential viass and associated differential striplines that travel through those tight via regions in print circuit boards are prone to high levels of crosstalk. This work investigates the far end crosstalk behavior from the via region and the pin area wiring and shows that crosstalk cancellation or mitigation can be achieved by super positioning crosstalk from these two sections. Electromagnetic modelling and signal integrity analysis are carried out to demonstrate that crosstalk cancellation can be done by controlling the length of the pin area wiring as well as other printed circuit board design properties.

Broadside-coupled differential routing is designed in via pin-fields for high-density packages. As compared with the standard edge-coupled differential routing, the proposed broadside-coupled routing reduces near-end crosstalk (NEXT) by nearly 10dB in the simulated 50GHz frequency range as a result of sixfold-widened inter-pair spacing in package breakouts. Other signal integrity (SI) properties including impedance matching, far-end crosstalk (FEXT), mode conversion and PN skew, are also characterized and compared. A design sizing shows that the proposed broadside-coupled configuration can use the same package construction as the edge-coupled counterpart and is an efficient approach that increases package routing density while maintaining desirable signal integrity for high-speed signals.

The characterization of the signal integrity (SI) performance of differential high-speed channels that have an imbalance due to mismatched via stub length is investigated. The impact of the asymmetric stubs are characterized with regards to impedance matching, differential-to-common mode conversion and intra-pair skew computation. Simulations for the short and long differential vias are carried out in both the frequency-domain and the time-domain with a back-drilling tolerance of ±10 mils for the residual stubs. It is shown that there is a 9 Ω differential impedance variation, over -40dB mode conversion loss above 5GHz and 2~3 ps of intra-pair skew is introduced. An example is illustrated to show the impact of the stub asymmetry for the high-speed channel with a time-domain eye simulation at 40 Gbps data rate. It is shown that the short imbalanced differential via with a 20 mil stub asymmetry has the eye diagram degradation in the peak-peak jitter that doubles the jitter for the channel with vias with equal-length residual stubs.

DDR5 Differential DIMM (DDIMM) is being defined in JEDEC and uses OMI as a host interface with the data transfer rate per data differential pair being specified at 25.6Gb/s minimum at present and at 51.2Gb/s maximum in the future. This is a significant data rate increase for DRAM modules over conventional single-ended data transferring DIMMs. For example, the DDR5 LRDIMM data transfer rate per pin is 3.2Gbps. This study utilizes the DDIMM early engineering samples with DDR4 to evaluate the OMI channel running at 25.6Gb/s. Validating the DDIMM PCB wiring for the high-speed differential memory bus requires accurate high-speed link simulations. These simulations require accurate models representing differential wiring in the DDIMM PCB stack up. The models must be built using not only representative physical dimensions but also accurate frequency dependent material properties obtained through PCB characterization. The simulation results of the initial study in 2018 similar to 19 concluded that the typical Copper Clad Laminate (CCL) and prepreg material used in the industry standard R/LR DIMM leads to signal integrity degradation relative to a better reference material at 25.6Gb/s OMI bus data rate[l]. This paper is based on 2019 similar to 20 DDIMM test results and the full channel time domain eye diagram analysis with BER at 10(boolean AND)-15 assuming an improved DDIMM PCB stack up with hybrid structure to satisfy signal integrity while minimize the material cost premium. DDIMM will be paired with the Storage Networking Industry Association (SNIA) SFF-TA-1002 high speed connector which differs significantly from the JEDEC RDIMM connector for improved electrical signaling characteristics. The connector to PCB interface design has been studied as it is of utmost importance for achieving good signal integrity[l]. The DDIMM test samples for this study include the high speed connector to PCB interface attributes such as Plated Through Hole (PTH) in ground contact pad, ground plane void under OMI signal pad and tie bar removal. The challenges of DDIMM PCB mechanical interaction with SFF-TA-1002 connector have been highlighted in the initial study[l]. This study uses early engineer samples to evaluate the insertion/extraction performance. Future work will use test vehicle of PCB/connector pairs to characterize the high speed electrical performance and evaluate the contact reliability. In summary, this paper presented the full channel simulation result assuming an improved DDIMM PCB material/stack-up at 25.6Gbps for comparison with the performance that baselined in the initial work with the industry standard PCB material. Physical characterization of the engineering samples has been conducted to baseline the DDIMM PCB to connector contact interface. Electrical test is performed with early engineering samples in IBM high speed system to verify the simulation result.

This work presents an NRZ receiver (RX) implementation for microprocessor application in 7nm FinFET CMOS technology. It covers data rate from 25 to 50Gb/s and features on-chip AC coupling to support a wide input common-mode range. The RX includes two identical banks with their own clock and data recovery (CDR) to dynamically tackle parameter drift over time. A quarter-rate 3-tap fully speculative decision feedback equalizer (DFE) opens eyes over channel with 30dB insertion loss. Current-mode logic (CML) based clock path boasts three degrees of freedom of phase adjustment and random jitter (RJ) attenuation to broaden the eyes. At 0.9V supply the energy efficiency is 2.22pJ/b with 28% eye opening (BER=10 -12 ) at 50Gb/s with PRBS31 and channel loss of 20dB.

A comprehensive signal integrity model to hardware correlation study on an improved, 44 Gb/s capable, hybrid land grid array (HLGA) socket connector design is presented. The connector only design SI performance is shown through 3D electromagnetic (EM) modelling. Details of the test vehicle designed to carry out the connector hardware evaluation are shown. Simulation modelling and experimental results of the test vehicle inclusive of the connector are presented and compared. The systematic testing ensures that the new component performs up to its required specifications which ensures successful operation at the system level.

While equalization is usually a positively contributing factor towards opening eye diagrams further, sometimes over equalization can occur and degrade an eye opening as opposed to improve it. This paper explores the effectiveness of using post-cursors FFE transmitter equalization on 25.78Gb/s communication links with different transmitter and receiver equalization. The effect is observed on two topologies with different loss levels and impedance profiles. Simulation and experimental results are presented and discussed.

A novel edge card connector design approach with tunable signal integrity (SI) properties is proposed. The tunability is achieved through the presence or absence of a grounded conductive fixture in between the connector pin rows. The main purpose of the tunability is to take an existing connector having a certain impedance intended to work in a high-speed link channel and be able to adjust the impedance of that connector for another channel requiring a different impedance. In this paper, the fixture is designed with a thin metal layer sheet expanding beneath a connector's pins to provide tunable capacitive coupling between the signal and the ground in order to effectively drop the connector's impedance from 100ohm to 85ohm. Additionally, it was observed that not only was the impedance tunability achieved for the assumed connector but also improvements in crosstalk and loss potentially extending the operational bandwidth of the connector to higher frequencies. The benefits of the proposed approach are verified by simulations in both frequency-domain and time-domain. A time domain eye simulation of a typical PCIe gen4 SerDes channel designed for 85ohm impedance to work at 16 Gbps shows eye opening improvements of 10.7% and 5.2%, respectively, for the eye height and the eye width when using the tuned connector with the proposed approach.

Effects of PCB wiring in tightly pitched module pin fields on high speed channel signal integrity are evaluated in this paper. Three different module orthogonal pin pitches are considered: 0.8mm, 1.06mm and 1.27mm. Each of the pin pitch scenarios is represented through corresponding PCB via and PCB pin area wiring models. Frequency domain SI metrics, at 16GHz, of a full end to end channel including the different tightly pitched module PCB wiring scenarios are quantified, compared and discussed. Additionally, full channel time domain eye simulations carried out at 32Gb/s are used to evaluate effects on eye opening and correlate with the frequency domain observations.

DDR5 Differential DIMM (DDIMM) is being defined in JEDEC and will be introduced to the market in 2020. DDR5 DDIMM uses OMI (OpenCAPI Memory Interface) as the host interface. On the DDIMM printed circuit board (PCB), the minimum data transfer rate per data differential pair over the OMI bus is 25.6Gbps. This is a significant data rate increase for DRAM modules over conventional single-ended data transferring DIMMs. For example, the DDR5 LRDIMM data transfer rate per pin is 3.2Gbps. Careful attention must be paid to the bill of materials of the DDIMM to control its cost towards general market acceptance of this new DIMM technology. As a result, it is desired to use standard loss FR-4 material to build the DDIMM PCB. Validating the DDIMM PCB wiring for the high-speed differential memory bus requires accurate high-speed link simulations. These simulations require accurate models representing differential wiring in the DDIMM PCB stack-up. The models must be built using not only representative physical dimensions but also accurate frequency dependent material properties obtained through PCB characterization. The Short Pulse Propagation (SPP) method will be used to extract PCB frequency dependent material properties. PCB suppliers usually have different Copper Clad Laminate (CCL) and prepreg material set selections largely due to the supplier relations. The test coupons of this study will be built using CCL and prepreg materials from two suppliers. System level differential memory bus simulation based on SPP characterization will be performed and the simulation results from different material/stack-up designs will be benchmarked. DDR5 DDIMM will be paired with the Storage Networking Industry Association (SNIA) SFF-TA-1002 high speed connector which differs significantly from the JEDEC RDIMM connector for improved electrical signaling characteristics. In this work, the SNIA high-speed connector to PCB interface design will be studied as it is of utmost importance for achieving good signal integrity. In addition to high speed signal integrity, the DDIMM PCB mechanical interaction with the SFF-TA-1002 connector is studied and it will be highlighted in this paper. The PCB mechanical outline design proposal is made to mitigate module/connector mechanical interference. To understand the PCB yield impact, DIMM PCB suppliers' process capabilities for critical feature/dimensions will be studied as well.

Printed circuit board (PCB) via fields can cause signal integrity (SI) degradation to high speed bus channel PCB wiring in the form of: differential to common mode conversion, crosstalk and impedance mismatch. This is especially the case when differential pairs are close to via anti-pads, when trying to manage multiple differential pairs in between two vias which are tightly pitched from each other and/or when PCB layer misregistration is considered. An electromagnetic modelling study is carried out in this paper where two differential pairs are wired in between two columns of vias. Different design parameters are varied including the pitch between the two via columns, the spacing between the differential pairs and the number of vias in the column. Observations are made based on the presented results furthering the understanding of the phenomena that takes place and towards better PCB design implementations.

The first-level package that contains the IBM POWER9 processor chip is designed to achieve the high computational performance needed for cognitive systems in a cost-effective design. The throughput data bandwidth of the POWER9 package for high-end scale-up systems is more than 1 TB/s, which is double the data bandwidth of the previous generation. This increase in bandwidth is achieved by introducing a dielectric with a loss tangent of 40% of the predecessor material, a C4 density increase of 15%, higher number of stacked vias to reduce jogging, and improved via pattern and placement to increase the frequency and density of signals. The cloud platform scale-out POWER9 package leverages the high-end and cognitive platform package attributes to maintain signal frequency while introducing novel chip-package-system co-design techniques. These design techniques were used to produce a well-balanced two-socket entry-level package with four build-up layers above and below the core, instead of six, resulting in a significant cost reduction from the previous generation while supporting the signal frequencies of POWER9. POWER9 systems are the first to offer 16-Gb/s PCIe Gen4 and 25.8-Gb/s open coherent accelerator processor interface that interconnect the processor to the I/O, networking, and accelerators required for systems in the cognitive computing era. In this paper, we present the material and wiring technology needed to achieve the signal performance up to 25.8 Gb/s per channel, the package physical attributes, and the chip-package-system co-design methodology to achieve the increased signal density, minimize the crosstalk, and maximize the frequency while reusing the package form factors of the previous generation, IBM POWER8.

This paper examines methods to electromagnetically model a hybrid land grid array (HLGA) connector and its associated printed circuit board (PCB) via individually with the goal of achieving the best correlation between their cascade and when modelled together as a single structure. The transition between the connector and the PCB via is of utmost importance as this is the location where the segmentation takes place. In this activity, the segmentation takes place on or close by the solder ball transitioning a signal between the two components. The solder ball location and any associated pads and/or dog-bone traces are becoming more worthy of attention as signal rise times decrease and data rates increase. Different excitation port setup techniques are considered at the transition. The signal integrity (SI) metrics of the cascaded models generated from each method tested are compared against a reference merged model. Due to differences observed between the cascaded and the merged models for one of the conventional modelling methods, a modelling correction method is investigated to achieve a closer match between cascaded and merged models.

Open Coherent Accelerator Processor Interface (OpenCAPI) is a new industry-standard device interface that enables the development of host-agnostic devices that can coherently connect to any host platform that supports the OpenCAPI standard. This in turn allows such devices to coherently cache host memory to facilitate accelerator execution, perform direct memory access and atomics to host memory, send messages and interrupts to the host, and act as a host memory home agent. OpenCAPI utilizes high-frequency differential signaling technology while providing the high bandwidth and low latency needed by advanced accelerators. OpenCAPI encapsulates the serializing cache access and address translation constructs in high-speed host silicon technology to minimize overhead and design complexity in attached silicon such as field-programmable gate arrays and application-specific integrated circuits. Finally, OpenCAPI architecturally ties together transaction layer, link layer, and physical layer attributes to optimally align to high serializer/deserializer (SerDes) ratios and enable high-bandwidth, highly parallel exploitation of attached silicon.

This paper explores a new passive coupling technique for multi-band high speed signaling in Substrate Integrated Waveguides (SIW). Two monopole antenna feeds operating at two different center frequencies are used for coupling signals into the SIW. Multiple antenna feeds can be obstructions to each other's radiation, thus degrading the quality of the SIW feed and as a result transmission through the SIW deteriorates significantly. In this paper, optimization of the feeds' relative locations is studied to achieve maximum power coupling into the SIW with minimum interference between the monopole feeds.