Automated coding style assessment tools are increasingly used in programming education; however, there is still limited understanding of how novice learners interact with and process the feedback they provide. To address this gap, this study presents a qualitative think-aloud investigation involving nine students from an introductory Python course. Using a purpose-built web-based tool, StyleLine, as a research instrument, we captured students’ real-time cognitive, behavioural, and affective responses to automated style feedback. The findings indicate a divergence between students’ positive self-reported perceptions and their observed behaviours during interaction with the tool. While questionnaire data suggested high satisfaction and usability, the qualitative analysis revealed several learning challenges, including a tendency toward non-iterative (“one-and-done”) revision, instances of task abandonment when encountering unclear feedback, and inconsistent transfer of learned concepts across tasks. This study contributes empirical insights into how novice learners engage with automated feedback and highlights the limitations of relying solely on self-reported measures. The findings also suggest that feedback designed for conciseness may increase cognitive processing demands for novices when insufficient scaffolding is provided. Overall, this study offers design implications for developing feedback systems that prioritise clarity and support novice learning more effectively.

The deployment of Low Earth Orbit (LEO) satellite constellations is an important step toward global-scale quantum networking. However, evaluating satellite quantum network protocols under spatiotemporal orbital dynamics and quantum physical constraints remains computationally expensive and challenging. In this paper, we propose QUASAR, a lightweight simulator for evaluating entanglement distribution in satellite-based quantum networks. QUASAR provides a decoupled architecture that integrates dynamic orbital topologies, time-varying optical transmittance, and quantum memory decoherence into network- layer attributes. To demonstrate its capabilities, we abstract and implement two representative hardware architectures: Simultaneous Downlink and On-Orbit Stitching. We further introduce an Entanglement Distribution Rate (EDR)-Aware Spatiotemporal Routing (EASR) heuristic as a reference workload. Our case study examines how QUASAR supports different satellite architectures, routing workloads, realistic orbital traces, concurrent requests, and scalable event-driven execution. With over 85

Multi-target tracking at extreme edge computing faces critical challenges, including excessive decision latency and target uncertainty due to resource constraints of extreme edge devices and observation heterogeneity. To address this, we propose a novel zero-shot multi-agent reinforcement learning (MARL) framework for multi-target tracking on heterogeneous extreme edge devices, called SmartHD. SmartHD features two innovative mechanisms, including a lightweight participation control mechanism that dynamically selects agents based on local computing resource availability and target uncertainty, enabling decentralized coordination to reduce latency, and a fully parameter-shared rotation control mechanism incorporating a contribution estimation block to handle agent heterogeneity and a relevant agent determination block to focus on critical observations. This design enables zero-shot generalization to unseen scenarios and eliminates retraining needs. Extensive evaluations demonstrate that SmartHD can effectively reduce decision latency by minimizing information dependencies and lowering target state uncertainty, achieving up to a 60.2 % performance improvement compared to the baselines.

Federated learning (FL) enables multiple participants to collaboratively train machine learning models while ensuring their data remains private and secure. Blockchain technology further enhances FL by providing stronger security, a transparent audit trail, and protection against data tampering and model manipulation. Most blockchain-secured FL systems rely on conventional consensus mechanisms: Proof-of-Work (PoW) is computationally expensive, while Proof-of-Stake (PoS) improves energy efficiency but risks centralization as it inherently favors participants with larger stakes. Recently, learning-based consensus has emerged as an alternative by replacing cryptographic tasks with model training to save energy. However, this approach introduces potential privacy vulnerabilities, as the training process may inadvertently expose sensitive information through gradient sharing and model updates. To address these challenges, we propose a novel Zero-Knowledge Proof of Training (ZKPoT) consensus mechanism. This method leverages the zero-knowledge succinct non-interactive argument of knowledge proof (zk-SNARK) protocol to validate participants' contributions based on their model performance, effectively eliminating the inefficiencies of traditional consensus methods and mitigating the privacy risks posed by learning-based consensus. We analyze our system's security, demonstrating its capacity to prevent the disclosure of sensitive information about local models or training data to untrusted parties during the entire FL process. Extensive experiments demonstrate that our system is robust against privacy and Byzantine attacks while maintaining accuracy and utility without trade-offs, scalable across various blockchain settings, and efficient in both computation and communication.

Medical images often contain sensitive information, and one typical security measure is to encrypt medical images prior to storage and analysis. A number of solutions, such as those utilizing deep learning, have been proposed for medical image encryption and decryption. However, our research shows that deep learning-based encryption models can potentially be vulnerable to backdoor attacks. In this paper, a backdoor attack paradigm for encryption and decryption network is proposed and corresponding attacks are respectively designed for encryption and decryption scenarios. For attacking the encryption model, a backdoor discriminator is adopted, which is randomly trained with the normal discriminator to confuse the encryption process. In the decryption scenario, a number of subnetwork parameters are replaced and the subnetwork can be activated when detecting the trigger embedded into the input (encrypted image) to degrade the decryption performance. Considering the model performance degradation due to parameter replacement, the model pruning is also adopted to further strengthen the attacking performance. Furthermore, the image steganography is adopted to generate invisible triggers for each image; subsequently, improving the stealthiness of backdoor attacks. Our research on designing backdoor attacks for encryption and decryption network can serve as an attacking mode for such networks, and provides another research direction for improving the security of such models. This research is also one of the earliest works to realize the backdoor attack on the deep learning based medical encryption and decryption network to evaluate the security performance of these networks. Extensive experimental results show that the proposed method can effectively threaten the security performance both for the encryption and decryption network.

One fundamental problem of content caching in edge computing is how to replace contents in edge servers with limited capacities to meet the dynamic requirements of users without knowing their preferences in advance.Recently, online deep reinforcement learning (DRL)-based caching methods have been developed to address this problem by learning an edge cache replacement policy using samples collected from continuous interactions (trial and error) with the environment.However, in practice, the online data collection phase is often expensive and time-consuming, thus hindering the practical deployment of online DRL-based methods.To bridge this gap, we propose a novel Agile edge Cache replacement method based on Offline-online deep Reinforcement learNing (ACORN), which can efficiently learn an edge cache replacement policy offline from a training dataset collected by a behavior policy (e.g., Least Recently Used) and then improve it with fast online fine-tuning.We also design a specific convolutional neural network structure with multiple branches to effectively extract content popularity knowledge from the dataset.Experimental results show that the offline policy generated by ACORN outperforms the behavior policy by up to 38%.Through online fine-tuning, ACORN also achieves the number of cache hits as good as that of several advanced DRL-based methods while significantly reducing the number of training epochs by up to 40%.

The recent breakthrough in Wireless Power Transfer (WPT) provides a promising way to prolong network lifetime by employing a charging vehicle to replenish energy. Data transmissions from nodes typically happen in response to physical sensory events, leading to time-varying energy consumption. To improve charging efficiency, the existing schemes collect energy information by employing a data-gathering vehicle or data collection protocol. However, in duty cycle networks, these schemes either incur extra vehicles or high data collection delay. To solve this problem, we propose an mobile adaptive charging scheme with rapid data sharing (rShare), which establishes multi-layer collection trees and collects overall energy data to the vehicle. A spatial predicted active sending (SPAS) algorithm is proposed for distant nodes to actively estimate the future position and transmit their data to cover potential positions of the charging vehicle, which significantly reduces data collection delay. We also propose an estimated time of arrival (ETA)-aware scheme based on the TSP Nearest Neighbor algorithm that updates the charging path based on the collected data. Extensive simulation results demonstrate that our scheme outperforms the state-of-the-arts in terms of dead node avoidance with less communication overhead.

Edge-AI, the convergence of edge computing and artificial intelligence (AI), has become a promising paradigm that enables the deployment of advanced AI models at the network edge, close to users. In Edge-AI, federated continual learning (FCL) has emerged as an imperative framework, which fuses knowledge from different clients while preserving data privacy and retaining knowledge from previous tasks as it learns new ones. By so doing, FCL aims to ensure stable and reliable performance of learning models in dynamic and distributed environments. In this survey, we thoroughly review the state-of-the-art research and present the first comprehensive survey of FCL for Edge-AI. We categorize FCL methods based on three task characteristics: federated class continual learning, federated domain continual learning, and federated task continual learning. For each category, an in-depth investigation and review of the representative methods are provided, covering background, challenges, problem formalisation, solutions, and limitations. Besides, existing real-world applications empowered by FCL are reviewed, indicating the current progress and potential of FCL in diverse application domains. Furthermore, we discuss and highlight several prospective research directions of FCL such as algorithm-hardware co-design for FCL and FCL with foundation models, which could provide insights into the future development and practical deployment of FCL in the era of Edge-AI.

Federated learning (FL) has shown its great potential for achieving distributed intelligence in privacy-sensitive IoT. However, popular FL approaches, such as FedAvg and its variants share model parameters among clients during the training process and thus cause significant communication overhead in IoT. Moreover, nonindependent and identically distributed (non-IID) data across learning devices severely affect the convergence and speed of FL. To address these challenges, we propose a communication-efficient FL framework based on Two-step Knowledge Distillation, Fed2KD, which boosts the classification accuracy through privacy-preserving data generation while improving communication efficiency through a new knowledge distillation scheme empowered by an attention mechanism and metric learning. The generalization ability of Fed2KD is analyzed from the view of domain adaption. Extensive simulation experiments are conducted on Fashion-MNIST, CIFAR-10, and ImageNet data sets with various non-IID data distributions. The performance results show that Fed2KD can reduce the communication overhead and improve classification accuracy compared to FedAvg and its latest variants.

During the past decade, Industry 4.0 has greatly promoted the improvement of industrial productivity by introducing advanced communication and network technologies in the manufacturing process. With the continuous emergence of new communication technologies and networking facilities, especially the rapid evolution of cellular networks for 5G and beyond, the requirements for smarter, more reliable, and more efficient cellular network services have been raised from the Industry 5.0 blueprint. To meet these increasingly challenging requirements, proactive and effective allocation of cellular network resources becomes essential. As an integral part of the cellular network resource management system, cellular traffic prediction faces severe challenges with stringent requirements for accuracy and reliability. One of the most critical problems is how to improve the prediction performance by jointly exploring the spatial and temporal information within the cellular traffic data. A promising solution to this problem is provided by graph neural networks (GNNs), which can jointly leverage the cellular traffic in the temporal domain and the physical or logical topology of cellular networks in the spatial domain to make accurate predictions. In this article, we present the spatial-temporal analysis of a real-world cellular network traffic dataset and review the state-of-the-art research works in this field. Based on this, we further propose a time-series similarity-based graph attention network, TSGAN, for the spatial-temporal cellular traffic prediction. The simulation results show that our proposed TSGAN outperforms three classic prediction models based on GNNs or GRU on a real-world cellular network dataset in short-term, mid-term, and long-term prediction scenarios.

As the number of mobile devices which is based on the Android system continues to grow rapidly, it becomes a primary target for security exploitation through undesirable malicious apps (malware) being unwittingly downloaded, which is often due to negligent user behavior patterns that grant unnecessary permissions to malicious apps or simply malware evolving to be sophisticated enough to bypass systematic detection. There have been numerous attempts to use machine learning to capture an application's malicious behavior focusing on features deemed to be germane to high security risks, but most of them typically focus only on a single algorithm, which is not representative of a huge family of ensemble techniques. In this paper, we develop an ensemble learning based malware detection approach for the Android system. To validate the performance of the proposed approach, we have conducted some experiments on the real world Android app dataset, which contains 3618 features that are initially obtained from the static, dynamic and ICC analyses. We then select 567 important features through feature selection. The overall detection accuracy is 97.73%, accompanied by a high 97.66% F-1 score that reflects a high relationship between precision (97.06%) and recall (98.28%). The experimental results clearly show that the ensemble learning based malware detection approach could effectively identify malware for the Android system.

The quest to democratize the use of Field-Programmable Gate Arrays (FPGAs) has given High-Level Synthesis (HLS) the final push to be widely accepted with FPGA vendors strongly supporting this VLSI design methodology to expand the FPGA user base. HLS takes as input an untimed behavioral description and generates efficient RTL (Verilog or VHDL). One major advantage of HLS is that it allows us to generate a variety of different micro-architectures from the same behavioral description by simply specifying different combination of synthesis options. In particular, commercial HLS tools make extensive use of synthesize directives in the form pragmas. This strength is also a weakness as it forces HLS users to fully understand how these synthesis options work and how they interact to efficiently set them to get a hardware implementation with the desired characteristics. Luckily, this process can be automated. Unfortunately, the search space grows supra-linearly with the number of synthesis options. To address this, this work proposes an automatic synthesis option tuner dedicated for FPGAs. We have explored a larger number of behavioral descriptions targeting ASICs and FPGAs and found out that due to the internal structure of the FPGA a large number of synthesis options combinations never lead to a Pareto-optimal design and, hence, the search space can be drastically reduced. Moreover, we make use of large database of DSE results that we have generated since we started working in this field to further accelerate the exploration process. For this, we use a technique based on perceptual hashing that allows our proposed explorer to recognize similar program structures in the new description to be explored and match them with structures in our database. This allows us to directly retrieve the pragma settings that lead to Pareto-optimal configurations. Experimental results show that the search space can be accelerated substantially while leading to finding most of the Pareto-optimal designs.

Over the past few years, fog radio access networks (F-RANs) have become a promising paradigm to support the tremendously increasing demands of multimedia services, by pushing computation and storage functionalities toward the edge of networks, closer to users. In F-RANs, distributed edge caching among fog access points (F-APs) can effectively reduce network traffic and service latency as it places popular contents at local caches of F-APs rather than the remote cloud. Due to the limited caching resources of F-APs and spatiotemporally fluctuant content demands from users, many cooperative caching schemes were designed to decide which contents are popular and how to cache them. However, these approaches often collect and analyze the data from Internet-of-Things (IoT) devices at a central server to predict the content popularity for caching, which raises serious privacy issues. To tackle this challenge, we propose a federated learning-based cooperative hierarchical caching scheme (FLCH), which keeps data locally and employs IoT devices to train a shared learning model for content popularity prediction. FLCH exploits horizontal cooperation between neighbor F-APs and vertical cooperation between the baseband unit (BBU) pool and F-APs to cache contents with different degrees of popularity. Moreover, FLCH integrates a differential privacy mechanism to achieve a strict privacy guarantee. Experimental results demonstrate that FLCH outperforms five important baseline schemes in terms of the cache hit ratio, while preserving data privacy. Moreover, the results show the effectiveness of the proposed cooperative hierarchical caching mechanism for FLCH.

VLSI design companies are now mainly fabless and spend large amount of resources to develop their Intellectual Property (IP). It is therefore paramount to protect their IPs from being stolen and illegally reversed engineered. The main approach so far to protect the IP has been to add additional locking logic such that the circuit does not meet the given specifications if the user does not apply the correct key. The main problem with this approach is that the fabless company has to submit the entire design, including the locking circuitry, to the fab. Moreover, these companies often subcontract the VLSI design back-end to a third-party. This implies that the third-party company or fab could potentially tamper with the locking mechanism. One alternative approach is to lock through omission. The main idea is to judiciously select a portion of the design and map it onto an embedded FPGA (eFPGA). In this case, the bitstream acts as the logic key. Third party company nor the fab will, in this case, have access to the locking mechanism as the eFPGA is left un-programmed. This is obviously a more secure way to lock the circuit. The main problem with this approach is the area, power, and delay overhead associated with it. To address this, in this work, we present a framework that takes as input an untimed behavioral description for High-Level Synthesis (HLS) and automatically extracts a portion of the circuit to the eFPGA such that the area overhead is minimized while the original timing constraint is not violated. The main advantage of starting at the behavioral level is that partitioning the design at this stage allows the HLS process to fully re-optimize the circuit, thus, reducing the overhead introduced by this obfuscation mechanism. We also developed a framework to test our proposed approach and plan to release it to the community to encourage the community to find new techniques to break the proposed obfuscation method.

Behavioral IPs (BIPs) have one salient advantage compare to the traditional RTL IPs given in Verilog or VHDL. The BIP can be used to generate RTLs with very different characteristics by simply specifying different synthesis directives. These synthesis directives are typically specified at the source code in the form of pragmas (comments) and control how to synthesize arrays (e.g. registers or RAM), loops (unroll or fold) and functions (inline or not). This allows a BIP consumer to purchase a BIP once and re-use it in future projects by simply specifying a different mix of these synthesis directives. This would obviously not benefit the BIP provider as the BIP consumer would not need to purchase the BIP again for future projects as oppose to IPs bought at the RT or gate-netlist level. To address this, this work presents a method to enable the BIP provider to lock the search space of the BIP such that the user can only generate micro-architectures within a specified search space. This leads to significant benefits to both parties: The BIP provider can now discriminate the BIP price based on how much of the search space is made visible to the BIP consumer, while the BIP consumer benefits from a cheaper BIP, albeit limited in its search space. This approach is made possible through partial encryptions of the BIP. Thus, this work presents a method that selectively fixes some synthesis directives and allows the BIP user to modify the rest of the directives such that the micro-architectures generated are guaranteed to be within the pre-defined search space.

Python's naming convention provides suggestions on naming style, but these suggestions are not always clear for beginners who struggle to understand the usefulness of the conventions. In this research, we studied two properties that affect naming, namely, name-length and style. We analyzed python code from five professional project libraries and compared the name statistics with those obtained from student code. Our results show that, compared to students' work, expert developers use longer names (more descriptive) and are more closely compliant with the existing python naming convention. This research provides specific recommendations on the length and style of naming integers, floats, data structures, functions, function arguments and classes for students of Python.

In this research, we developed a methodology for automatic evaluation of coding style and estimate its effectiveness compared to human evaluation. To achieve this, we developed 179 features spanning 8 categories to capture code structure and other stylistic properties. Results based on a set of student assignments and code from a Python textbook validate the features as effective in classification tasks. The features were further used to optimise classifiers to predict the teacher’s evaluation of the student code and obtain good classification accuracy. The proposed feature set and experimental results provide a first step towards providing students with automatic coding style feedback.

Raising the level of VLSI design abstraction from the register transfer level (RTL) to the behavioral level has multiple advantages: 1) It reduces the turn-around-time; 2) allows faster verification; and 3) extends the reusability of the design as high-level synthesis (HLS) automatically reoptimizes the synthesized circuit when new process technologies are available by simply selecting a different technology library. Moreover, HLS makes extensive use of synthesis directives that control how to synthesize mainly loops (unroll or pipeline), arrays (register or RAM), and functions (inline or not). This further increases the reusability of the behavioral code as it enables the generation of micro-architectures with different area versus performance tradeoffs. These advantages open the door to third-party IP (3PIP) vendors providing behavioral IPs (BIPs). Unfortunately, the market of third-party BIPs is still very small and mostly limited to the HLS vendors themselves. Being so flexible is also their main weakness as it makes them only economically viable if the BIP provider can charge a large premium as it is highly unlikely that the BIP consumer will require their service again. Traditional IP vendors discriminate the price of the IP based on the amount of flexibility of the IP, e.g., RTL description versus providing a synthesized gate netlist. We envision a similar price discrimination strategy for BIPs by limiting the reusability of the BIP by partially encrypting the BIP source code. The main idea is to limit the search space, and hence, the reusability of the BIP such that it only allows the BIP consumer to generate micro-architectures within a predefined search space range. This is accomplished by selectively fixing some of the synthesis directives in the form of pragmas at the source code while leaving others explorable. By encrypting the portion of the BIP that contains the fix pragmas we can guarantee that no designs outside of the predefined search space are generated. We believe that this work could serve as catalyst to grow the BIP market.

With the massive deployment of 5G cellular infrastructures, traffic prediction has become an indispensable part of the cellular resource management system in order to provide reliable and fast communication services that can meet the increasing quality-of-service requirements of smart city. A promising approach for handling this problem is to introduce intelligent methods to implement a highly effective and efficient cellular traffic prediction model. Meanwhile, integrating the multiaccess edge computing framework in 5G cellular networks facilitates the application of intelligent traffic prediction models by enabling their implementation at the network edge. However, the data shortage and privacy issues may still be obstacles for training a robust and accurate prediction model at the edge. To address these issues, we propose a data-augmentation-based cellular traffic prediction model (ctGAN-S2S), where an effective data augmentation submodel based on generative adversarial networks is proposed to improve the prediction performance while protecting data privacy, and a long-short-term-memory-based sequence-to-sequence submodel is used to achieve the flexible multistep cellular traffic prediction. The experimental results on a real-world city-scale cellular traffic dataset reveal that our ctGAN-S2S model achieves up to 48.49% improvement of the prediction accuracy compared to four typical reference models.