Single-crystalline molybdenum disulfide (MoS2) emerges as a leading n-type channel material for high-performance electronic devices in the angstrom era of computing. Chemical vapor epitaxy of single-crystalline MoS2 relies on sapphire template engineering to impose a preferred crystalline orientation. A challenge of these approaches is to control the within-wafer statistical variance of the MoS2 orientation when sapphire substrates are manufactured to semiconductor industry-standard specifications and wafer size. Here, we report single-crystalline MoS2 on sapphire by metal-organic chemical vapor deposition (MOCVD), a mainstream semiconductor manufacturing method, without relying on template-engineering. By lowering the precursor adsorption rate in the mass-transport-limited reaction regime, the MoS2 nucleation and growth rate slows sufficiently to favor epitaxy, initially with 0° and 60°-oriented crystals. Although a minority of 60°-oriented crystals deposit, a single-crystalline MoS2 monolayer forms through recrystallization of 60°-oriented domains during and after MoS2 monolayer coalescence. As a result, single-crystalline 1.1 MoS2 monolayer exhibits carrier mobilities of 30 ± 5 cm2V-1s-1 in transistors fabricated through a 300 mm bonding-to-wafer route. Recrystallization during chemical vapor epitaxy presents a key mechanism to modulate crystal defect structures in transition metal dichalcogenides and is compatible with both bonding-to-wafer and monolithic integration approaches.

We study the effect of high-k dielectric scaling and annealing treatments on the reliability of 300-mmintegrated WS2 field-effect transistors (FETs). Under positive gate bias stress, devices featuring a 1.5nmAlOx/1+3nmHfO2 top-gate stack exhibit a significantly lower number of active defects compared to those with 1.5nmAlOx/8+3nmHfO2 or 1.5nmAlOx/3+3nmHfO2. The improvement is most pronounced in the low-stress bias regime, where the HfO2 defect band dominates device degradation. Transient TCAD simulations incorporating a non-radiative multiphonon model underscore two main factors behind this stability enhancement: fewer available defects in the thinner HfO2 layer, and a reduced defect density arising from either partial curing of plasma-induced defects or the preserved amorphous nature of the scaled HfO2. In addition to gate oxide scaling, we assess two annealing strategies: an H2S anneal performed prior to AlOx deposition, and a high-pressure (HP) H2 anneal applied post-fabrication. The HP H2 anneal yields the greatest stability enhancement, achieving an approximately twofold reduction in active defect density. These results provide insight into the development of reliable 2D FETs using industry-standard oxides.

As logic scaling enters the angstrom era, vertically stacked complementary field-effect transistors (CFETs) based on atomically thin two-dimensional (2D) semiconductors offer a potential route to extend device scaling beyond the A2 node. Here, we develop an A2-oriented 2D CFET integration flow with a CPP of 36 nm and Lg of 10 nm and present initial demonstrations of several key process modules. Despite their atomically thin channels, 2D GAA CFETs do not provide a contacted poly pitch scaling advantage over Si GAA CFETs at the A2 node, because contact formation constraints impose a similar minimum CPP of 36 nm. We also combine a critical assessment with a multiscale power-performance-area (PPA) evaluation framework spanning quantum transport simulations, compact-model generation, A2-targeted 2D CFET gate-all-around (GAA) integration-flow definition, parasitic extraction and circuit-level benchmarking. Our analysis, however, shows that the expected benefits of 2D GAA CFETs are strongly constrained by non-idealities, in particular high contact resistance and dominant layout-induced parasitic capacitances. Although architectural optimization can improve the Ieff/Ceff ratio, the associated rise in absolute capacitance limits circuit-level gains. Meaningful progress will require co-optimization of contacts, transport and parasitics, together with 2D-specific CFET architectures.

We present our efforts to facilitate 300mm MX2 growth on sapphire and completely automate the layer transfer module. Two concepts are presented; a collective die-to wafer approach (CoD2W), and a 300mm wafer-to-wafer approach (W2W), both with the vision of enabling MX2 integration in foundries for BEOL and/or FEOL applications.

A fully recoverable leakage behaviour is observed near the source side of two-dimensional (2D) back gate HfO2 oxide field-effect transistors (FETs) when subjected to a gigapascal -level mechanical stress (MS) applied locally via a nanoindenter tip. Due to the asymmetrical device structure of 2D-FETs, the generated stress is distributed non-uniformly, with maximum compressive stress concentrated near the source 'S' terminal rather than the drain 'D' terminal. Among the studied channel lengths (L similar to 0.135 mu m to L similar to 10 mu m), longer channels exhibit higher stress near the source terminal than the drain side, attributed to proximity effects under a constant applied load. An increase in gate leakage current with increasing MS is consistently observed, suggesting the generation of shallow traps. At the same time, the apparent reduction in the band gap lower the barrier for electron emission, giving rise to behaviour that appears consistent with a low-voltage dependent Poole-Frenkel mechanism approaching ohmic characteristics. Notably, upon removal of the MS, the gate leakage fully recovers. These findings underscore the mechanical sensitivity of HfO2 gate dielectrics in 2D TMDs semiconductor devices and provide new insights into MS-induced reliability concerns, as well as the potential for mechanically changed electronic responses.

In this work, we present, for the first time, a stacked 2D nanosheet FET featuring a gate-all-around (GAA) and top-gate architecture with monolayer $\text{MoS}_{2}$ channels. Additionally, a gate-last process is introduced to scale down nanosheet FETs to a channel width of 40 nm without inducing damage to the $\text{MoS}_{2}$ monolayer. For the first time, conformal gate stack deposition on monolayer $\text{MoS}_{2}$ is achieved without an interfacial layer. The electrical performance of the devices is systematically evaluated in terms of device yield, subthreshold slope (SS), and on/off current ratio. This successful demonstration of 2D nanosheet FETs highlights their strong potential as fundamental building blocks for future 2D CFET applications.

The continuous expansion of two-dimensional materials research since the first developments of over 15 years ago has enabled tremendous progress in the fundamental understanding of their properties and behavior. The promises held by these materials to facilitate scaling beyond silicon-based device architectures are still valid, but the manufacturability and integration with silicon technology remain challenging. On the metrology side, characterization of the device channel and assessment of the expected performance is lacking, at least in a fully non-destructive and process line-compatible implementation. The current paper demonstrates a clear correlation between metrics associated with the transistor performance on one hand, and parameters from photoluminescence spectra on the other. The concept is demonstrated on state-of-the-art 300 mm process MoS2 devices, without the need for specific measurement conditions or sample preparation. Being truly non-contact and relatively fast, this analysis provides the community with a potential route toward non-invasive material quality assessment, applicable at several stages of the process and with a direct connection to device performance.

A fully recoverable leakage behaviour is observed near the source side of two-dimensional (2D) back gate HfO 2 oxide field-effect transistors (FETs) when subjected to a gigapascal -level mechanical stress (MS) applied locally via a nanoindenter tip. Due to the asymmetrical device structure of 2D-FETs, the generated stress is distributed non-uniformly, with maximum compressive stress concentrated near the source ‘S’ terminal rather than the drain ‘D’ terminal. Among the studied channel lengths ( L ∼ 0.135 μ m to L ∼ 10 μ m), longer channels exhibit higher stress near the source terminal than the drain side, attributed to proximity effects under a constant applied load. An increase in gate leakage current with increasing MS is consistently observed, suggesting the generation of shallow traps. At the same time, the apparent reduction in the band gap lower the barrier for electron emission, giving rise to behaviour that appears consistent with a low-voltage dependent Poole–Frenkel mechanism approaching ohmic characteristics. Notably, upon removal of the MS, the gate leakage fully recovers. These findings underscore the mechanical sensitivity of HfO 2 gate dielectrics in 2D TMDs semiconductor devices and provide new insights into MS-induced reliability concerns, as well as the potential for mechanically changed electronic responses.

Recent advances in fabricating field-effect transistors with MoS2 and other related two-dimensional (2D) semiconductors have inspired the industry to begin with the integration of these emerging technologies into FAB-compatible process flows. Just like in the lab research on 2D devices performed in the last decade, focus during development is typically put on pure technology-related issues, such as low-temperature growth methods of large-area 2D films on target substrates, damage-free transfer from sacrificial substrates and growth of top-gate oxides. With maturing technology, the problem of stability limitations caused by oxide traps is gradually coming into focus now. Thus, here we report an in-depth analysis of hysteresis and bias-temperature instabilities for MoS2 FETs fabricated using a 300 mm FAB-compatible process. By performing a comprehensive statistical analysis on devices with top gate lengths ranging between 18 nm and 10 μm, we demonstrate that aggressive scaling results in additional stability problems, likely caused by defective edges of the scaled top gates, in particular at higher operation temperatures. These are important insights for understanding and addressing the stability limitations in future nanoscale 2D FETs produced using FAB process lines.

CFETs based on 2D materials hold the potential to replace Si as a channel at advanced technology nodes. In this work, gate-all-around (GAA) nanosheet FETs with the monolayer MoS2 channels are presented. The MoS2 monolayer was successfully suspended above the oxide trench of varying lengths. Less than 20% sag was observed up to a trench length of 200 nm. For the first time, a gate-first process, in combination with critical point drying, is introduced to scale down GAA nanosheet FETs to 50 nm channel width and length without introducing damage to the monolayer MoS2. Perfect conformal gate stack deposition on the monolayer MoS2 sheets is achieved by using TMA 'soaking' treatment. The successful demonstration of monolayer GAA 2D nanosheet FET further shows high potential as a basic component for the future 2D CFET chips integration.

Defective grain boundaries form in semiconductors when deposition approaches do not control crystal grain orientation. This poses existential limitations to fabricating highly performing semiconductor devices with two-dimensional semiconductors for industry’s future Angstrom technology nodes. Today’s monolithic or bottom-up deposition methods do not control crystal grain orientation on industry-standard substrates covered with amorphous dielectrics due to lack of crystallographic symmetry provided by the substrate. Here, we report selective artificial chemical vapor epitaxy of tungsten disulfide (WS2), an approach to orient two-dimensional crystals on amorphous substrates with nanopatterns. Amorphous nanopatterns with axial symmetry that mimics the trigonal crystallographic symmetry of the WS2 crystal lattice guide WS2 crystal orientation as well as location. We show a proof of concept in a 300 mm industrial pilot-line at back-end-of-line compatible deposition temperature. This monolithic concept opens possibilities to eliminate grain boundaries and deposit single-crystalline two-dimensional materials directly on conventional amorphous dielectrics at feature scales relevant for most advanced device architectures.

In this work, a self-consistent method is used to identify and describe defects plaguing 300 mm integrated 2D field-effect transistors. This method requires measurements of the transfer characteristic hysteresis combined with physics-based modeling of charge carrier capture and emission processes using technology computer aided design (TCAD) tools. The interconnection of experiments and simulations allows one to thoroughly characterize charge trapping/detrapping by/from defects, depending on their energy position. Once the trap energy distribution is extracted, it is used as input in transient TCAD simulations to reproduce the experimental hysteretic transfer characteristics. Our method is widely applicable to any 2D channel/gate stack combination. Here, it is demonstrated on FAB-integrated devices with AlOx/HfO2 gate oxide. A Gaussian-approximated defect band in the AlOx interlayer centered at a position of about 0.1 eV below the conduction band minimum of WS2 is obtained. Based on this energy position, it is concluded that aluminum interstitial and oxygen vacancies are the defects giving rise to the observed hysteresis. These defects are detrimental to the stability of the studied devices as they are easily accessible by channel carriers during on-state operation. A prominent hysteresis obtained during measurements is consistent with this conclusion.

We demonstrate a low-temperature automation-compatible, and reproducible 300mm MX2 dry transfer process. We have successfully transferred 300mm WS2 in a repeatable process flow with >99.5% morphological yield. In-FAB integrated transistors fabricated via this route have >99% electrical yield on best wafers and is comparable to that obtained from analogous direct-grown WS2 integrated wafers. Further, we also demonstrate back-EOT scaling down to 2nm that is otherwise out of scope via high temperature direct growth. This transfer process facilitates a viable route to implement scaled MX2 devices for FEOL CFET, and BEOL active circuits.

In this work, stacked nanosheet FETs with monolayer MoS2 channels are presented. At a channel length of 40 nm, the transistor exhibits a remarkable $\mathrm{I}_{\text{ON}}-451\ \mu \mathrm{A}/\mu \mathrm{m}$ at $\mathrm{V}_{\text{DS}}=1\ \mathrm{V}$, achieved with two tiers of monolayer-MoS2 channels. The device has a record $\mathrm{I}_{\text{ON}}/\mathrm{I}_{\text{OFF}} > 10^{9}$ and a yield of 96.59%, which shows good electro-static control in the nanosheet channels. We compare these results to dual gate 2D FETs and show how learnings on the planar devices can be utilized in a gate-all-around case. The successful demonstration of stacked 2D nanosheet FETs with high performance further extends Moore's Law scaling with the future 2D CFETs application.

Evidence of microscopic inhomogeneities of the side source/drain contacts in 300 mm wafer integrated MoS2 field-effect transistors is presented. In particular, the presence of a limited number of low Schottky barrier spots through which channel carriers are predominantly injected is demonstrated by the dramatic current changes induced by individual charge traps located near the source contact. Two distinct types of "contact-impacting traps" are identified. Type-1 trap is adjacent to the contact interface and exchanges carriers with the metal. Its impact is only observable when the adjacent contact is the reverse-biased FET source and limits the channel current. Type-2 trap is located in the AlOx gate oxide interlayer, near the source contact, and exchanges carriers with the channel. Its capture/emission time constants exhibit both a gate and drain bias dependence due to the high sensitivity of the contact regions to the applied lateral and vertical fields. Unlike typical channel-impacting oxide traps, both types of reported defects affect the Schottky barrier height and width rather than the threshold voltage and result in giant random telegraph noise (RTN). These observations indicate that the contact quality and geometry play a fundamental role in the ultimate scaling of 2D FETs.

Direct two-dimensional (2D) material growth is widely considered as the preferred 2D integration approach due to its simplicity and cost-effective fabrication flow. On the other hand, a 2D transfer route enables full wafer-scale integration of epitaxial 2D material and can facilitate new device possibilities. However, the transfer of a wafer size atomically thick 2D material from a growth to a device wafer often seems an impossible hurdle to overcome, since a 2D material is strongly influenced by strain and its surroundings. Moreover, the stability of some of these 2D materials is a concern as several are prone to oxidation. Here, an overview is given of the current state-of-the-art 2D material transfer techniques and an outlook is presented to improve these transfer processes further to achieve a reliable FAB compatible epitaxial 2D transfer.

Inspired by techniques designed for 3D integration, a die-to-wafer (D2W) transfer method can enable MX 2 -channel devices in a semiconductor fab for either high-performance CFET or hybrid-integrated CMOS. A Collective D2W(CoD2W) technique was successfully developed to transfer epitaxial single-layer MX 2 from sapphire to 300mm device wafers which facilitates uniform and residue-free “dies”. We report a FEOL semiconductor compatible integration flow used to build back-gated transistors with high device yield and mobility values up to 50 cm 2 /Vs on SiO 2 back gate dielectrics.