This work investigates the anomalous decrease in subthreshold swing (SS) with decreasing channel length observed in poly-Si thin-film transistors (TFTs) with an undoped channel. Simulation analysis is performed on poly-Si TFTs and devices built on silicon-on-insulator to understand the reason behind this observation. The results indicate that this phenomenon is closely related to defects in the grain boundaries (GBs) of the poly-Si channel. For poly-Si TFTs, modulation of the channel potential relies on increasing the gate bias to induce charges for filling the GB traps. Since a portion of the traps in the source/drain junctions has been charged, it facilitates the modulation of the channel potential. As the channel is shortened, the fraction of the depletion regions of the junction in the channel increases, leading to a reduction in SS.
Thin-film transistors (TFTs) featuring ultrathin (approximate to 3 nm) indium gallium oxide (InGaO) channels synthesized by atomic layer deposition (ALD) with systematically varied In:Ga ratios (30%-90% In) were studied. A tradeoff between threshold voltage (V-T) and field-effect mobility (mu(FE)) is observed with varying In content in the channel. As the In-content reaches between 60% and 75%, the device changes from enhancement mode to depletion mode. By adding an O-3 treatment after source/drain formation, the devices exhibited significant enhancement in subthreshold characteristics and stability. Notably, the 90% In-content TFT evolves from nonideal to excellent ON-OFF characteristics, exhibiting a subthreshold slope as low as similar to 65 mV/dec. Meanwhile, mu FE increases monotonically with increasing In concentration, reaching a maximum of 47.1 cm(2)/V s for the device with a 90% In-content channel after O-3 treatment. The linear correlation between mu FE and 1/RCH verifies that the enhancements of mu FE with In-content result dominantly from intrinsic channel conductance. Positivebias-stress (PBS) stability is dramatically improved after O-3 treatment. Threshold voltage shifts (triangle V-T) after stressed at V-G = V-T + 3 V for 3600 s are 9 and 64 mV for channels with 60% and 75% In-content, respectively. These findings underscore the potential of combining compositional engineering and O-3 treatment to achieve high-performance and stable oxide TFTs for future low-power electronics.
Membrane-based CO2 capture has emerged as a promising solution to mitigate global climate change. In this study, outside-in three-layer Pebax/PDMS/PSU composite hollow fiber membranes (HFMs) were developed for CO2/N2 separation, guided by a bottom-up design strategy. To minimize the transport resistance of PSU substrates and intrusion of gutter-layer solutions, the effects of PSU concentration, nonsolvent additives, and bore-fluid composition during the spinning of hollow fiber substrates were systematically investigated. The optimized PSU substrate enabled the formation of PDMS/PSU composite HFMs exhibiting a high CO2 permeance of approximately 4400 GPU with a CO2/N2 selectivity of 10.69 in pure-gas tests. Subsequently, the Pebax selective layer was deposited onto the PDMS gutter layer via dip coating, with precise control over plasma activation, withdrawal speed, and Pebax concentration to regulate surface wettability and coating hydrodynamics. Under optimal conditions, the resulting Pebax/PDMS/PSU HFMs achieved a CO2 permeance of 1366 GPU and a CO2/N2 selectivity of 24.50 at a Pebax concentration of 0.40 wt%, and a CO2 permeance of 1075 GPU and a CO2/N2 selectivity of 31.97 at 0.45 wt%. Importantly, the optimized membranes also demonstrated stable separation performance under mixed-gas (15/85 CO2/N2) and humid conditions, delivering CO2 permeances of 1106 and 859 GPU with corresponding CO2/N2 selectivity of 22.26 and 28.32 for 0.40 and 0.45 wt% Pebax coatings, respectively. This work highlights a scalable strategy that integrates the engineering of substrate morphology with hydrodynamics of selective-layer coating, providing an efficient way to develop next-generation composite HFMs for post-combustion CO2 capture.
An area-efficient physical layout for a 1T ROM array with robust VSS mesh and coding procedure are proposed in this study. A 1.8 -Mbit 1CPP ROM macro on $2-\text{nm}$ Nanosheet logic CMOS technology shows the record bit-density of $160.7 \text{Mbit} / \text{mm}^{2}$ and access speed of 513 ps, as well as maximum operational frequency and active power are improved by 10.6% and 8.4% from the baseline layout, while suppressing the peak IR drop comparable to the baseline.
In this study, the characteristics of the grain boundaries of β-Sn grains in micro-Cu-pillar/Sn–Ag–Cu solder/Cu-pad joints were investigated through 110 and 100 pole figure analyses and Euler mapping. The twist and tilt grain boundaries and the corresponding rotation axis were identified, and the contour separation method and axis distribution analysis were employed to calculate the twisting and tilting angles, which were determined to be 38.54° ± 0.90° with rotation axis of < 2 3 0 > (Δ = 2.38° ± 0.08°) and 56.22° ± 0.27°with rotation axis of < 041 > (Δ = 3.82° ± 0.09°), respectively. The twist grain boundaries exhibited rapid migration toward the outer surfaces of the micro-solder bumps and eventually disappeared during aging. By contrast, the tilt grain boundary remained stable after 75 h of aging at 140 ℃, extending transversely through the solder bump. In addition, the stable tilt grain boundary was determined to be a twin grain boundary with a < 041 > axis and a 101 twin plane. The shift of the rotation axis in the 101 twin from the < 010 > direction can be identified by the < 041 > pole figure with shift angle of 7.9° ± 2.5° (Δ = 3.82° ± 0.09°); however, the 101 twinning plane still remains.
