This paper addresses the challenge of partial task offloading in multi-user, multi-server Mobile Edge Computing (MEC) networks, where each wireless device (WD) can split its task into two components: one executed locally and the other offloaded to a selected edge server. The objective is to minimize the weighted sum delay across all users by optimizing both the binary offloading decisions and the continuous resource allocations. We propose a two-step solution framework (DNNOPPO): first, a deep neural network (DNN) is trained to predict the binary offloading decisions based on system input features including channel gains and task weights. Second, given the predicted offloading configuration, a convex subproblem is solved to determine the optimal task splitting ratio and CPU resource allocation at edge servers. The DNN is supervised using data generated from convex-relaxed optimization solutions, ensuring that the learned model generalizes toward delay-efficient offloading. Simulation results validate that the proposed method achieves near-optimal performance while significantly reducing computation time, demonstrating its practical utility in real-time MEC scheduling.
Heart disease is one of the leading causes of death worldwide. A heart disease patient monitoring and surveillance system is an important approach to real-time monitoring of cardiac health. This study develops a Wireless Body Area Network (WBAN) for a heart disease monitoring system using an AD8232 sensor for electrocardiography (ECG) detection with an ESP32-C6 microcontroller for wireless transmission via Wi-Fi, Bluetooth Low Energy (BLE), and Zigbee. The efficiency of the proposed system is measured based on data loss and transmission time, with results showing that Bluetooth offers the highest ECG classification accuracy, particularly with the Random Forest machine-learningbased classification model. A real-time visualization app was also developed using MIT App Inventor. These findings support the development of portable heart monitoring devices for improved patient care and disease prevention.
The increasing demand for high-performance computing (HPC) necessitates architectures that efficiently manage data-intensive workloads while optimizing memory access and communication overhead. Applications such as scientific simulations, deep neural networks and multimedia processing require scalable and high-bandwidth interconnect solutions to sustain performance. This paper introduces HIIM-NoC (Hybrid Interconnect and Intermediate Memory-Based Network-on-Chip), an improved 2.5D NoC architecture designed to enhance latency, bandwidth, and power efficiency for HPC applications. HIIMNoC employs a hybrid interconnect topology, combining double butterfly, folded torus, and mesh architectures, alongside strategically placed intermediate memory modules, to facilitate efficient on-chip data movement and workload distribution. Experimental evaluations show that HIIM-NoC reduces dynamic power consumption by 7.85% and improves runtime performance by up to 19%, demonstrating its scalability and efficiency for nextgeneration HPC workloads.
Recently, demands and usages of artificial intelligence are growing more and more. The various of electrical computation devices, such as mobile devices, are being built with AI technology. But the AI operation's load is very heavy. The AI data processing method, usually a convolutional neural network, mainly consists of the matrix convolution and the matrix multiplication-actually, they are the same effective, depending on how the operation sequences are arranged. The matrix multiplication is not suited to sequential data processing. During matrix convolution or matrix multiplication, the memory access pattern is non-linear. This is difficult to use the parallelized data processing and, actually, the original sequential processor has limit hardware unit resources for parallelized data processing. Even in sequential processing, the non-linear access pattern needs a conditional branch test and jump instruction for address calculation. Eventually, these situations induce large power consumption and poor performance during AI operation. Therefore, it is necessary that the appropriate hardware-software system, that system is the matrix structure planarize to linear access and uses the parallel data processing based on MAC tile, is implemented for efficient AI algorithm computation. In this paper, a parallel data processing structure based on systolic tile array is used for fast operation time and efficient ALU resources usage in matrix multiplication. For enhanced data processing throughput, the proposed new accelerator is equipped with a heavier processing element-(PE) tile than the original systolic tile PE, making it possible to calculate the multi state partial sums at once. Reordering multidimensional matrix as a linear planarization matrix array is also proposed at the micro-architecture level for diminishing the nonlinear access address calculation. The accelerator's memory system enables multiple elements to commit and reduces the data access times to DRAM memory during operation. In conclusion, this proposal accelerator ends up performing AI CNN operations much faster, with low power consumption.
A two-wheeled self-balancing robot or TW-SBR is an automatically operated machine that stands on two wheels. The simple structured TW-SBRs are used as educational material in control engineering. In this paper, we propose an affordable and user-friendly TW-SBR using an FPGA named robbit to promote the adoption of robots and contribute to FPGA education and research. By using a low-end FPGA board and inexpensive and commercially available parts, we lower the barrier of hardware costs, and by leveraging a framework for FPGA development named CFU proving ground, we reduce the technical hurdles. We detail the design and implementation of robbit. Furthermore, through a quantitative comparison with a TW-SBR utilizing the ESP32-C3 microcontroller board, we demonstrate the stability and utility of robbit. Additionally, we show the effectiveness of robbit by showing a discussion of hardware costs, assembly time, and applications of robbit.
