The thermal concept of the electronic package for high power devices needs to address the increased temperature of operation and the need to insure the head dissipation of the device. In common Fan-out packages Epoxy Mold compounds (EMC) are used which is not well adopted to high temperature operation as EMC has a low thermal conductivity. In this paper the research on the development of a Fan-Out Wafer Level Package is described. First a FEM simulation comparing a Mold compound and SiC Fan-out Packages was performed. It showed that the thermal resistance of the package can be reduced by 72% allowing up to 20 W/mm2 eight times power loss in a 3.9 mm2 package. Later a manufacturing process was developed for this SiC Fan-out Wafer level Package which suits for high power application addressing. For this package Wafer Level bonding techniques of SiC Wafers are used to embed the active chip, e.g. a Monolithic Microwave Integrated Circuit (MMIC). Through SiC Vias (TSiCV) are used to realize the backside contacts and a SiC nanoparticle filled adhesive is used to inprove the thermal conductivity of the bond interface.
This work demonstrates wafer-level thin film encapsulation (TFE) [1], [2] of a radio-frequency microelectromechanical systems (RF MEMS) device with rerouting of contacts and pads for flip-chip compatibility to a much smaller CMOS chip. RF MEMS devices are a key market driver for growth in the MEMS industry. This article enunciates the optimization of lithography steps in defining redistribution layers (RDL) and opening bond pads on high topography RFMEMS wafer to reduce RC delay and match bond pad locations for Heterogeneous integration of MEMS with ASIC.
Silicon Carbide (SiC) based power modules are widely used in the 5G communications, electric vehicle, aerospace, marine, energy and other industrial fields. Different from the consumer electronics application, automotive grade SiC power devices are operation with higher junction temperature, higher power density, higher switching frequency, and harsher environment, the reliability of the power module is particularly important. Power cycling testing is one of the critical tests used for the reliability assessment of the power semiconductor devices and power module development. Power cycling test periodically applies a current to the devices integrated in the power module. This leads to power loss in the entire module and results in a rise in the temperature of the power devices, as well the ununiformed temperature distribution in the power module. In this paper, thermal analysis is conducted for a 6-in-1 double side cooling SiC power module. The temperature distribution of the power module is simulated and the junction temperature of the SiC power devices in the power module is analyzed. The junction temperature difference under different power cycling test conditions is evaluated, and final test condition of the power cycling test for the developed 6-in-1 power module is proposed.
In this study, the low cycle shear fatigue performance and fracture behavior of microscale ball grid array (BGA) structure Cu/Sn–3.0Ag–0.5Cu/Cu solder joints with various shear amplitudes were systematically investigated at different current densities by experimental, theoretical methods and finite element analysis. The experimental results showed that the fatigue life of the solder joint decreased with increasing shear amplitude and current density. The descent rate of fatigue life decreased with increasing shear amplitude at the same current density. Moreover, the deterioration of current stressing on the fatigue life of the solder joint was more serious at the lower shear amplitude. In addition, with increasing current density, the solder joint fracture position transitioned from the solder matrix to the solder/IMC layer interface, and the shape of the fracture path shifted from arc-shape to flat-shape.
Board level reliability, such as solder joint reliability under temperature cycling, is essential requirement for electronic packages. At the design stage, many optimization methods are adopted like geometry, structure, and materials. Finite element analysis (FEA) is a powerful and efficient tool to assess reliability performance. However, FEA simulation is still time-consuming for numerous DOE runs. In this study, combining statistical software and FEA analyses, regression equation is generated for quick assessment on solder joint reliability (SJR) by choosing an example of effect of solder joint shape on SJR performance. Interaction of different parameters can be considered in the equation. This provides an efficient and accurate methodology for design optimization and improvement with saving cycle time for new product introduction (NPI). Such methodology can be extended to other areas to make design-for-reliability more robust and efficient.
