Severe thermal accumulation and localized hotspots in conventional polydimethylsiloxane (PDMS) encapsulation can limit the performance of high-power light-emitting diodes (LEDs) incorporating colloidal quantum-dots (CQDs). To address these packaging-induced limitations, this study proposes an advanced encapsulation architecture utilizing a porous collagen scaffold. By replacing the continuous-phase PDMS with a three-dimensional porous matrix, the proposed strategy may spatially separate CQD-containing regions, mitigating clustering-related non-radiative heat generation. Three packaging configurations-a conventional CQD/PDMS reference, an ultrasonically dispersed CQD/collagen composite, and a novel sequentially dispensed CQD/collagen structure-are systematically fabricated and evaluated. Thermal characterization demonstrates that the sequentially dispensed collagen architecture reduced the macroscopic hotspot observed in the CQD/PDMS reference and reduced the peak package surface temperature by up to 10 °C compared to the PDMS baseline. Under identical CQD loading conditions, the collagen-based packages achieved color conversion efficiency (CCE) enhancements approaching 45%. These improvements are attributed to the synergistic effects of altered CQD-related heat-source distribution, reduced local thermal concentration, and package-level heat spreading within the porous network. Furthermore, the proposed sequentially dispensing process is compatible with standard LED packaging processes, offering a potentially scalable thermal-management strategy for next-generation optoelectronic devices.
The increasing power density and integration level of advanced electronic devices have made effective thermal management of multi-source electronic systems increasingly critical. Multi-evaporator pumped two-phase cooling loops have emerged as promising solutions to address these challenges. However, their startup reliability under unequal thermal loading remains unclear. This study experimentally investigates the dynamic startup characteristics of a dual-evaporator pumped two-phase cooling loop under unequal heat loads. A heat-load-distribution-based startup regime map is established to identify different startup behaviors and reveal the impact of thermal imbalance on transient cooling performance. The results show that three distinct startup modes, including synchronous, asynchronous, and coupled modes, sequentially occur with increasing heat-load difference between the two evaporators. In the synchronous startup mode, both evaporators demonstrate a twice-rise overshoot startup, although the upstream evaporator experiences a slight delay in reaching steady-state. In the asynchronous mode, the high-heat-load and low-heat-load evaporators exhibit twice-rise overshoot startup and gradual startup behaviors, respectively. In the coupled mode, after reaching peak temperatures, the wall temperatures of two evaporators display a two-step descending response, indicating entry into a two-phase unstable region. Within the tested conditions, the steady-state temperature difference between the two evaporators increases with total heat flux in the synchronous and asynchronous modes, whereas it decreases in the coupled mode. These findings provide insights into the transient thermal reliability of multi-evaporator pumped two-phase cooling systems and offer design guidelines for stable thermal management of high-heat-flux electronics.
Through-passivation vias (TPVs) enable vertical interconnection through thick BEOL passivation layers in heterogeneous integration schemes. While thermo-mechanical reliability of package-level through-vias, including TSVs and through-package vias, has been extensively investigated in the context of 3D integration and interposer technologies [1], [2], [3], the reliability of sub-micron through-passivation vias embedded in BEOL passivation stacks remains largely unexplored. In this work, TPV reliability is investigated using a combination of electrical testing, failure analysis, and finite-element modelling. Via diameter is systematically varied across the wafer using lithography exposure-dose modulation while maintaining an otherwise identical process flow. Electrical daisy-chain measurements show a pronounced increase in failure probability for smaller TPV diameters. Failure analysis reveals nanoscale interfacial gaps at the via bottom, consistent with stress-induced delamination. Finite-element simulations attribute this behaviour to residual thermo-mechanical stresses generated during cooldown from tungsten deposition, which increase strongly as via diameter decreases. A generalized Brewer–Lagacé quadratic delamination criterion is applied for the first time to via/metal routing layer interfaces and successfully captures the observed diameter-dependent failure trend. TPVs fabricated within an optimized diameter range exhibit stable electrical performance under reflow, temperature cycling, and high-humidity stress conditions. These findings establish lithography-driven TPV diameter optimization as an effective strategy for improving robustness of BEOL through-passivation vias without altering materials or process integration. In addition, this work extends the Brewer–Lagacé quadratic delamination criterion, originally developed for laminated composite structures, to the via/metal layer interface encountered in advanced semiconductor manufacturing. The resulting framework provides a practical method for linking TPV geometry, thermomechanical stress, and electrical failure probability.
This paper presents a contact degradation assessment method for 10 kV switchgears based on dual inductive coupling broadband impedance measurement. Theoretical models and simulations in CST Studio Suite (Computer Simulation Technology) are established for switchgear tulip contacts to analyze how contact misalignment (axial insertion-depth deficiency) and corrosion reshape the impedance spectrum. A non-intrusive insitu measurement chain is developed with dual inductive coupling probes and a vector network analyzer (VNA). The device-under-test input impedance ZDUT of the lead–tulip (or switchgear primary-loop) assembly is recovered after calibration; by comparing the variation trends of the equivalent inductance LM and the first resonant frequency f0 obtained from ZDUT, tulip-contact degradation is assessed qualitatively. Sample-level experiments and switchgear platform tests are conducted for two representative faults, namely moving-stationary contact misalignment and tulip contact aging induced by salt-spray exposure. Results show a quasi-linear relationship between impedance features and fault severity, with consistent trends between measurement and simulation for the same asset geometry. Relative to conventional dc loop resistance tests, broadband impedance features can provide complementary early indicators of microscopic interface deterioration and therefore support overheating risk screening and targeted maintenance of distribution network switchgears.
