SiC MOSFETs offer significant advantages over their silicon counterparts, including higher breakdown voltage, faster switching speed, and better thermal conductivity, making them well-suited for high-frequency, high-voltage, and high-temperature applications in power electronics. Nevertheless, the long-term reliability of SiC MOSFETs remains a major challenge, as device failures can lead to system-level malfunctions, unplanned outages, and elevated safety risks, particularly in mission-critical applications. To assess their reliability under typical converter stresses, a hybrid-active neutral point clamped (H-ANPC) inverter is used. The H-ANPC inverter efficiently balances switching losses and thermal stress, providing higher efficiency and better thermal management, making it ideal for high-power applications requiring robust, long-term reliability. This article proposed an active gate voltage control (AGVC) technique, which is used to develop a scheme for optimizing gate voltage to improve the reliability and lifetime of SiC MOSFETs within the H-ANPC inverter. To determine the lifetime models of SiC MOSFETs in the H-ANPC inverter, two accelerated tests (ATs), the inverter-like accelerated test (IAT), and the time-dependent dielectric breakdown (TDDB) test are applied. Although the IAT-based lifetime model indicates SiC MOSFET reliability, gate voltage variations make it crucial to assess impacts on gate oxide degradation by the TDDB-based lifetime model. The article includes detailed explanations of the experimental setups for IAT, TDDB, and the H-ANPC inverter, along with an analysis of the results and lifetime modeling. Also, the AGVC scheme (AGVCS) is tested within the IAT framework, and results are provided. Together, these insights highlight strategies for enhancing the reliability and lifetime of SiC MOSFETs in H-ANPC inverter applications.
The repetitive short-circuit (R-SC) endurance of asymmetrical trench SiC MOSFETs is characterized through a maximum likelihood Weibull statistical framework with 90% Fisher-information confidence intervals, applied to a test matrix spanning two DC-link voltages (400V and 600V), six pulse durations per voltage, and four case temperatures (25, 75, 100, and 125°C) at two selected operating points. The Weibull shape parameter β as a function of pulse duration is identified as a quantitative statistical signature of the underlying degradation behavior, with a strictly monotonically decreasing β(tp) profile at 400V (verified by the Mann–Kendall trend test at the 1% significance level) and a non-monotonic profile at 600V featuring a local minimum within the degradational regime followed by a sharp rise within the catastrophic transition window. The temperature-dependent analysis reveals a sign reversal of the pairwise apparent activation energy of the scale parameter at both operating conditions, with global linear Arrhenius regression coefficients of R2=0.164 and R2=0.528 that rule out a single-Arrhenius lifetime model over the tested case-temperature range. Post-stress transfer characteristics provide an independent electrical signature: the change in subthreshold swing and the threshold-voltage shift follow qualitatively different pulse-duration dependences, which a single trapped-charge population could not produce. The convergence of these complementary signatures — voltage-dependent β(tp) profile, sign reversal of the pairwise activation energy, quantile-dependent power-law exponent, and the divergent evolution of the two static-parameter metrics — is consistent with two competing degradation mechanisms whose relative weight depends on pulse duration, applied voltage, and case temperature. The engineering implication is that the population spread quantified by the B99/B1 ratio reaches a factor of 30.3 at 400V and 14µs, requiring derating prediction based on the lower-tail percentile rather than on the median in regimes of strong β(tp) decline.
Reconfigurable antennas rely fundamentally on their switching elements, whose operational lifetime, failure physics, and reliability govern real-world viability across applications from cognitive radio to vehicle-to-everything (V2X) communication and beyond-5G phased arrays. Despite extensive literature on antenna topology and electromagnetic performance, a unified comparative reliability analysis spanning all principal switching technologies does not exist. This paper presents the first such framework, covering seven quantitatively benchmarked technology classes — PIN diodes, varactor diodes, RF MEMS, field-effect transistors (FETs), optical switches, liquid crystals, and graphene — plus a qualitative treatment of memristive switches as an emerging eighth candidate, with eight original contributions: (i) an expanded literature synthesis identifying prior reliability gaps; (ii) quantitative characterisation of switching speed, cycle lifetime, failure modes, and mean time to failure (MTTF); (iii) failure-physics modelling including electromigration, time-dependent dielectric breakdown (TDDB), Coffin–Manson fatigue, and dielectric charging; (iv) a cross-technology reliability ranking grounded in failure physics; (v) a four-part Monte Carlo simulation with 105-sample Weibull failure-cycle distributions, temperature-dependent RON degradation trajectories, and V2X cumulative failure probability curves, calibrated against published experimental data; (vi) a multi-factor parametric sensitivity study; (vii) an application-specific selection matrix with deployment case studies; and (viii) a dedicated, quantitative treatment of RF power handling and hot-/cold-switching reliability across all technologies, a factor identified as a transversal reliability discriminator independent of the specific switching mechanism. Results show semiconductor diodes offer the most mature reliability profiles (>109 cycles), RF MEMS delivers superior insertion loss (0.1–0.3dB) but its endurance is strongly dependent on switching conditions, RF power, and device architecture, with substantial degradation under hot switching, and emerging materials (liquid crystals, graphene, memristive oxides) define the frontier for sub-terahertz operation and non-volatile switching, albeit with reliability databases still too immature for quantitative MTTF projection. Under a conservative 10Hz constant-rate stress envelope, Monte Carlo simulation predicts 50% cumulative RF-MEMS failure within 52 days, rendering them contraindicated for high-duty-cycle vehicular deployments unless operated under cold-switching protection. A future research roadmap for reliability-aware reconfigurable antenna design is presented.
This paper presents a mission profile (MP)-based reliability analysis framework for GaN-based power converters used in high-performance applications such as electric vehicles, renewable energy systems, and consumer electronics. GaN-based converters offer high efficiency, high power density, and the capability to operate at high switching frequencies. However, their long-term reliability and failure mechanisms have not yet been fully explored. Reliability analysis techniques developed for conventional Si-based converters are not directly applicable to GaN-based converters due to their distinct material properties and operating characteristics. In addition, although SiC devices belong to the wide-bandgap semiconductor family, their reliability evaluation approaches differ from those required for GaN-based converters. This study provides a systematic overview of MP-based reliability assessment methods for GaN-based converters. Various approaches for lifetime prediction are examined, and the associated challenges in applying these methods to GaN systems are discussed. The key factors influencing converter lifetime, including switching stress, MP variations, PCB parasitics, and operating conditions, are identified. The proposed approach enables an improved understanding of system-level reliability and supports the development of more accurate lifetime prediction methodologies for GaN-based power converters.
The spiking neural network (SNN) uses discrete spikes exploiting parallel, event-driven computations to process large amount of digital data, replicating the behavior of human brain. The SNN circuit has a leaky-integrate and fire (LIF) neuron and resistive RAM (RRAM) synaptic array with in-situ weight update through spike timing-dependent plasticity (STDP) mechanism. The single event transients (SET) due to particle strikes are major reliability threat for high speed integrated circuits. The effect of single event transients (SET) in 1T-1R RRAM synaptic array and CMOS LIF neuron circuit are analyzed in this paper. The SET due to single and multiple strikes create additional spikes and timing variations in the output spikes and affect the pattern/digit recognition. The RRAM synapses in SNN are implemented using Stanford RRAM model and the effect of parameter variations in the discrete output spikes are analyzed. The mitigation techniques to suppress the SET and model parameter variations in SNN circuit are proposed.
