The fatigue life of solder balls in Ball Grid Array (BGA) packages of a Printed Circuit Board (PCB) assembly is a key factor that influences the reliability of electronic devices. This study explores three novel methods to enhance the fatigue life of the PCB assembly with BGA packages, focusing on stress reduction techniques in solder balls under random vibration.The numerical analysis of the PCB assembly examined stress distributions and identified optimal design strategies to improve resistance to fatigue under random vibration. The findings demonstrate that strategic positioning of BGA packages, the use of additional supports, and modifications to PCB assembly can significantly reduce stress on solder balls, thus extending their fatigue life 8 to 10 times that of the existing design.
With the growing demand for high-safety and high-energy-density energy storage systems, all-solid-state lithium batteries (ASSLBs) have attracted extensive attention due to their excellent safety and potential high performance. Among them, the solid electrolyte is a key component. This study systematically investigates the effects of Li3AlF6 as a sintering aid on the sintering behavior, crystal structure, microstructure, and electrochemical performance of LLNO (Li0.25La0.25NbO3) ceramics. LLNO ceramic samples with different Li3AlF6 doping levels (0-8 wt.%) were prepared via a solid-state reaction method and sintered at 1050 degrees C and 1100 degrees C. The samples were characterized by XRD, SEM, AC impedance spectroscopy, and DC polarization testing. The results indicate that Li3AlF6 significantly reduces the sintering temperature of LLNO and promotes the densification process. However, excessive doping (8 wt.%) leads to the formation of impurity phases such as AlF3, increases grain boundary resistance, and reduces ionic conductivity. The sample with 5 wt.% Li3AlF6 sintered at 1050 degrees C exhibits the best overall performance: an ionic conductivity of 2.08 & times; 10(-6) S & centerdot;cm(-1) and an activation energy of 0.340 eV. Although its conductivity is slightly lower than that of pure LLNO (4.12 & times; 10(-6) S & centerdot;cm(-1)) sintered at 1100 degrees C, the introduction of Li3AlF6 provides a feasible route for low-temperature sintering, which is beneficial for future co-sintering integration with electrode materials.
The present work investigates the long-term relaxation behavior of anomalous photovoltage and photoelectret voltage in polycrystalline CdTe:Ag thin films prepared by oblique thermal evaporation.The relaxation kinetics were studied at room temperature under controlled photopolarization conditions. Experimental results reveal a pronounced two-stage relaxation behavior, consisting of a fast initial component with characteristic times of 2-4 min and a slow long-term component extending up to 25-45 min. The short-term relaxation is attributed to shallow trapping centers located near the band edges, while the long-term relaxation is governed by deep trapping centers associated with impurity-defect complexes involving silver atoms and cadmium vacancies. The observed metastable photoelectric states are explained within a bulk trapping model combined with near-surface band bending effects, which lead to asymmetric photocarrier separation and long-lived charge retention. The obtained results provide new insight into defect-controlled relaxation processes in CdTe:Ag thin films and demonstrate the crucial role of deep trapping centers in the formation and stability of photoinduced electric states. These findings are relevant for optimizing the photoelectric performance and long-term stability of CdTe-based photovoltaic and optoelectronic devices.
Phase-Frequency Detector (PFD) and Charge Pump (CP) are crucial components in Phase-Locked Loops (PLL) and Delay-Locked Loops (DLL), significantly impacting synchronization accuracy and system stability. In this paper, a new PFD based on dynamic logic with a minimal number of devices is designed, providing low delay and proper logic output levels. Additionally, a novel CP employing the gain-boosting technique and utilizing a cascode amplifier is proposed, achieving higher DC-gain and better current matching.The proposed design aims to minimize power consumption to the microwatt level, reduce circuit area, and achieve an operating frequency up to 3 GHz. Simulation results in 180-nm CMOS technology using Cadence software demonstrate that the proposed circuit offers lower power consumption, smaller area, and improved dynamic performance compared to conventional designs, making it well-suited for PLL and DLL applications in high-frequency communication systems.
Active noise cancellation (ANC) is an essential feature of audio equipment that reduces unwanted background noise. Unwanted signals in information bearing-signal referred to as noise, could degrade the strength of signals in terms of intelligibility and quality. Over the decade, various researchers developed different algorithms to enhance speech signal quality and for noise reduction. To address the issue, a Multitude Active Noise cancellation using White Shark Optimized Convolutional neural network-Long short-term memory Network (MANC Net) has been proposed. Initially, Dual Tree Complex Wavelet Transform (DTCWT) is utilized to enhance the quality of audio signal with a multitude noise and the signal features are extracted using a community detection based Genetic Algorithm. Afterward based on extracted signal, interference and desired signals are classified using Hybrid Convolutional neural network-Long short-term memory (CNN-LSTM). Additionally, the hyperparameters of CNN-LSTM are tuned using White Shark Optimization (WSO) for better accuracy. The efficiency of the proposed method is evaluated using accuracy, specificity, sensitivity, Normalized Mean Squared Error (NMSE), Short-Time Objective Intelligibility (STOI), and Perceptual Evaluation of Speech Quality (PESQ) parameter values in comparison with other conventional methods. The higher accuracy rate and low NMSE in the classification of audio signals evidenced the efficacy of the proposed MANC Net model. The overall accuracy of the proposed is 9.1%, 8.7%, 7.9%, 3.4%, and 1.5% better than Filtered-X Least Mean Square (FxLMS), deep Active Noise Cancellation (deep ANC), Construction Site Noise Network (CsNNet), Multi-Channel Active Noise Cancellation (MCANC), and Generative fixed-Filter Active Noise Control (GFANC), respectively.
Approximate Computing (AC) enables energy-efficient and high-performance computation for error-resilient applications such as data analytics, image processing, and multimedia. With the growing demand for low-power, high-density storage in Artificial Intelligence and Machine learning applications, researchers are exploring emerging technologies like FinFETs, memristors, Carbon Nano Tube FET(CNTFET), and Quantum-dot Cellular Automata (QCA) to mitigate the constraints of CMOS scaling. This paper proposes an efficient majority logic design using hybrid memristor-CMOS technology for low-power arithmetic applications. A power-efficient 1-bit adder, comprising three majority gates and one inverter, is designed and compared with existing memristor-based adders.Three Approximate Adder designs such as MAA1, MAA2, and MAA3 are implemented in 8-bit fully approximate ripple carry structure and 8-bit error-tolerant ripple carry structure, integrating four approximate and four accurate adders. Circuit performance, including power and delay, is analyzed using Cadence Virtuoso, where MAA1 achieves the lowest Power-Delay Product (PDP) in both structures. Image quality metrics, assessed using MATLAB with 8-bit pixel depth images, indicate that MAA3 attains the highest Peak Signal-to-Noise Ratio (PSNR) in the fully approximate structure. Error analysis using Verilog coding shows that the proposed MAA2 design achieves a 24.12% error rate reduction in the error-tolerant structure compared to its fully approximate counterpart, demonstrating its efficiency in balancing accuracy and power consumption.
Scintillator detectors, widely used in nuclear medicine and industrial applications such as radiation monitoring and material analysis, are sensitive to both neutrons and gamma rays (n/gamma). A key challenge in neutron detection is minimizing gamma-ray interference to ensure accurate measurements. Neutron-gamma discrimination is difficult because the two particle types often produce overlapping signals in scintillator detectors, with similar pulse amplitudes but subtle differences in shape and timing. Traditional methods struggle to distinguish these subtle features, leading to misclassification and reduced detection accuracy.To address this, we propose a deep neural network (DNN)-based approach combined with pulse shape discrimination (PSD) techniques to achieve high-precision particle discrimination in mixed n/gamma fields. Leveraging DNN's ability to learn complex patterns, our method effectively classifies neutron and gamma-ray pulses.The trained DNN model was evaluated against traditional discrimination algorithms, including the charge comparison method, rise-time analysis, frequency-domain gradient analysis, and K-means clustering. Quantitative results demonstrate a discrimination accuracy of 99%, significantly outperforming conventional techniques. Furthermore, the proposed DNN method not only enhances discrimination reliability in mixed radiation fields but also reduces processing time compared to existing methods, making it suitable for real-time applications in medical imaging and industrial neutron detection.
Accurate, field-ready timing and motion capture are essential for assessing agility beyond the limits of manual stopwatches. We present a modular measurement system that fuses infrared (IR) optical gates for robust event detection with a trunk-worn inertial measurement unit (IMU) for kinematic profiling. Each sensing node is built on an Adafruit Feather M0 Wi-Fi microcontroller and communicates via UDP to a laptop server. Time alignment is accomplished without internet connectivity: the server establishes a relative epoch and executes a triple-handshake broadcast protocol, while timestamps are generated at the edge to avoid latency bias from transport or processing. Module- and device-level characterization shows that IR-receiver processing combined with interrupt service routine latency yields a per-event timestamp error of 0.54 ms +/- 0.14 ms (latency +/- uncertainty), and local clocks remain stable over the durations relevant to agility trials. In wireless operation, accepted synchronization attempts form tight response clusters in favorable RF conditions, whereas congested environments may require retries; for section times across different gates we therefore report a conservative inter-node uncertainty. End-to-end validation across laboratory, entry-hall, and gym venues using the Agility T-test confirms that total test time measured on the same start/finish gate remains below 1 ms error over 10-20 s trials. Synchronized IMU waveforms add explanatory value beyond total and split times by revealing braking, change-of-direction, and re-acceleration phases. The system provides a deployable workflow with substantially improved precision over manual timing. Future work will target more robust synchronization and expanded analytics, including automated phase detection, asymmetry indices, and optional integration with indoor positioning
Delay Targeted Networking (DTN) facilitates communication in environments with sporadic connectivity and long delays, such as space missions and isolated locations. The rise of 5G technology has increased the demand for in-flight services, challenging aviation communication to provide reliable data through satellite systems and traditional macro-cellular networks. However, airborne communication's dynamic nature poses significant challenges, including irregular connections and variable delays.To tackle these challenges, a novel Smart Prediction and trAnsmission mechanism for delay taRgeted networK (SPARK) technique has been proposed to enhance the efficiency and reliability of DTNs in aviation communication.The proposed SPARK method includes a comprehensive node trust evaluation system, utilizing direct and indirect trust metrics to ensure network reliability. After evaluating node trustworthiness, the proposed method restricts heavy load traffic based on trustworthiness.The Prediction and Transmission Module incorporates the Cooperative Watchdog System (CWS) to dynamically update each node's reputation score. Nodes are classified into cooperative, partially cooperative, neutral, mislead, and selfish nodes. Experimental results demonstrate the effectiveness of the suggested SPARK framework utilizing evaluation parameters including delivery rate, delay, overhead, hop count, throughput, complexity, and resource utilization. The delay rate of the proposed SPARK method is 18.67%, 19.87%, and 14.45% is lower than the existing OPRNET, IDRL, and CCMA, techniques respectively. The distribution of the proposed SPARK framework attains a forwarding rate of 11% for selfish, and 9.2% for misleading based on their packet forwarding behavior.
The need for portable devices with high precision has raised the demand for optimization of power and delay in various dynamic comparator topologies. In this paper, an efficient architecture that does timely yet rapid comparison with reduced power dissipation and optimal energy per comparison is proposed. Introducing an extra tail transistor in preamplifier of comparator, assists in holding the high gain, thereby reducing delay as well as power. The latch is meanwhile ready with a minimum threshold value at its output nodes with the help of a pass transistor in between latch output nodes. The conventional, hybrid, and proposed architecture, namely Low power Rapid Charge Holding Dynamic Latched Comparator (LRCHDLC) are simulated and verified for power, delay, and energy efficiency in Cadence Virtuoso Spectre. The proposed technique shows a significant improvement in delay and power consumption when compared to conventional comparators. Monte Carlo simulation shows that the proposed technique is robust to the process mismatch, sustaining optimal power, delay and energy efficiency.
In Modern world, Fifth Generation (5G) technology is ubiquitous, so it is necessary to meet all of its service requirements. Hence, resource allocation for every service is very important. This research addresses the problem of resource allocation for both Enhanced Mobile Broadband (eMBB) and Ultra Reliable Low Latency Communication (URLLC) users.The work comprises both static and dynamic resource allocation for eMBB and URLLC users. This research aims to minimize latency for URLLC users by taking into account the time and energy constraints of both eMBB and URLLC in static resource allocation, formulating these constraints as a convex optimisation problem. The results show that the static resource allocation strategy performs better than the fixed bandwidth and Central Processing Unit (CPU) cycle schemes. However, the use of static resource allocation becomes inefficient as the number of users increases. We propose a dynamic resource allocation strategy to address this issue, which uses online conformal prediction to schedule URLLC traffic on top of eMBB. The dynamic resource allocation strategy outperforms all previous resource allocation methods, ensuring 67% eMBB efficiency and 1 millisecond latency for URLLC users.
As the demand for efficient and high-performance power electronic devices continues to grow, wide bandgap (WBG) semiconductors have emerged as a promising solution due to their superior characteristics. However, realizing their full potential requires not only the development of advanced semiconductor materials but also the optimization of packaging techniques. This paper examines the crucial role of packaging in leveraging the benefits of WBG devices, with a particular focus on mitigating inductance and addressing other critical concerns. Drawing from previous research and discussions, we explore various strategies to minimize inductance effects, enhance thermal management, ensure reliability, and optimize electrical performance. Through an interdisciplinary approach that encompasses electrical engineering, materials science, and mechanical engineering principles, this paper highlights the latest advancements in WBG device packaging, providing valuable insights for researchers and engineers working towards more efficient and reliable power electronic systems.
A frequency reconfigurable antenna for wireless applications using a fractal antenna structure is proposed. The fractal antenna is composed of a step resonator type which has a mirror image at the vertical axis in the top with a slit and a parallel mirror image at the vertical axis in the bottom without a slit. The resonating frequency of the fractal antenna is controlled by a Positive- Intrinsic-Negative (PIN) diode.Two PIN diodes are connected between the top and bottom of the fractal antenna. With the varying capacitance effect, the four possible modes of operation of the diode are obtained at the dual resonating frequency of 2.7 and 3.2 GHz.The proposed design holds significant potential for applications in Fifth Generation New Radio (5G NR) n1 band, and Wireless Fidelity (Wi-Fi) access points due to its small size and easy control mechanism. The Specific Absorption Rate (SAR) values were analyzed and are within the safety limits.
Mobile Edge computing (MEC) enables network functions and control programmable and operates key constituents of social networks in terms of increasing user's support on devices to carry out compute. It requires traffic offloading and task scheduling to improve the storage and fast computing. In this paper, a novel method, including data driven traffic modeling enabled by a Reinforcement learning algorithm (RLTOA), is proposed for offloading traffic and improving the computing speed and minimizing the application latency of the social network. The result of the proposed data driven modeling is compared with existing methods and validate how the data driven traffic modeling for providing the computation offloading service in terms of energy budget and the mobile drop and execution of edge server.The presented computation offloading, and energy management solutions can provide valuable perceptions for practical applications of MEC. Extensive numerical findings are presented to endorse the efficacy of RLTOA and display the effect of the social network requirement.
This study explores the influence of nitrogen gas flow rate on the electrical characteristics of indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) annealed under heat-assisted UV illumination.The aim is to understand how nitrogen flow rates impact the performance of solution-processed IGZO TFTs annealed at low temperatures, which is crucial for developing highperformance devices for next-generation electronics and temperature-sensitive applications. The IGZO TFTs were fabricated on glass substrates using a bottom-gate top-contact configuration, with the IGZO thin film deposited by inkjet printing and annealed in a chamber with varying nitrogen gas flow rates (0.5, 1, 2, and 5 L/min) at 250 degrees C for 2 hours under UV illumination. The electrical characteristics were extracted from transfer characteristics measurements. The results show that a nitrogen flow rate of 1 L/min enhances the electrical properties of IGZOTFTs, likely due to a suitable concentration of oxygen vacancies. Excessive N2 flow rates (>1 L/min) negatively impact on theTFT characteristics, while lower flow rates (<1 L/min) result in more negative threshold voltages and lower on/off current ratios. The study concludes that optimizing the nitrogen gas flow rate is critical for achieving desired TFT properties, offering a valuable tool for fine-tuning IGZOTFTs to meet specific application requirements.
This paper proposes multiband antenna-based Metamaterial (MTM) for beam splitting and gains improvement. Here, the focus is on developing the smart antenna using a Metamaterial Superstrate technique for modern wireless applications. The proposed antenna consists of two patches, the first one has a square shape placed on a Taconic FR-30 substrate, followed by the second patch constructed as a meander ring with two stubs for increasing the generated frequency bands. At the end of the design process, the proposed patch seems U-shaped to ensure the antenna beam is splitting at the desired frequency bands. In addition, the capacitive coupling is used for exciting the second patch, whereas the first patch is excited by conduction with a 50 Omega discrete port. Furthermore, a metasurface layer is designed and mounted on the second patch as a superstrate to increase the antenna gain toward the bore-sight direction.The results show a maximum gain of 8 dBi at 4.2 GHz with maximum dimensions of 108 x 108 mm2. Moreover, this antenna operates at additional frequency bands (2.6 GHz, 4.2 GHz, and 5.6 GHz), with a minimum reflection coefficient of-16.8 dB,-12.3 dB, and-30.6 dB, respectively. The proposed antenna is designed and analyzed using the CST MWS simulator.
chaotic systems offer benefits in diverse domains, including encryption and communication systems, particularly in the upkeep of intricate and safeguarded systems.This study introduces a new hyperchaotic system with four dimensions (4D), seven parameters, and four quadratic non-linear terms. An extensive analysis is conducted on the suggested hyperchaotic system to investigate its dynamic properties, such as chaotic attractors, stability of equilibrium points, spectrum of Lyapunov exponents (LE), bifurcation diagram, etc. The proposed system is validated both by experimental tests using an embedded hardware STM32 microcontroller and MATLAB simulations. The microcontroller-based chaotic systems proposed in the literature and the given hyperchaotic system in this study are compared in a tabular form. The outcomes of these trials constantly correspond, offering theoretical validation for the utilization of this hyperchaotic system in real-world applications. An application example of an autonomous mobile robot (AMR) driven by the presented hyperchaotic system is provided in this work, as efficient and fast terrain exploration is a crucial problem in AMR path planning research.
This paper presents the design of a MISO (multiple-input single-output) universal biquad filter in 130 nm CMOS UMC technology. The proposed filter consists of three operational transconductance amplifiers (OTAs), two grounded capacitors and one inverter stage. The topology, which has three inputs and one output, operates in all modes: voltage, transconductance, current, and transresistance. In addition, the filter generates all types of transfer functions (LP, HP, BP, BS, and AP). First, the filter topology with an inverter at the output is designed and analyzed in detail. Next, an improved topology with a differential amplifier as the output stage is proposed. The designed filter has a cutoff frequency of approximately 250 MHz and a current consumption of 4.5 mA. The impact of process, temperature, and voltage variations is examined through corner analysis.
This article presents a 5G millimeter Wave bandpass filter using air-gapped structure, which is fabricated through highprecision micro electromechanical system (MEMS) process.The grounded and open stub lines, as well as impedance transformation stub lines, which generating four transmission poles (TPs) and two transmission zeros (TZs), are proposed to achieve the design goal. FourTPs support a 24.25-27.5-GHz passband, while two TZs provide a sharp out-of-band rejection. Step-to-step design process is given to guide the 24.25-27.5-GHz bandpass filter design.The 24.25-27.5-GHz bandpass filter is fabricated and measured, which has a minimum insertion loss of 0.9dB within the passband.
Polar codes are among the most efficient types of error correction coding. Currently, these codes are employed in 5G communication networks and are the leading contender for 6G. Symmetry is significant in coding and decoding techniques for polar codes. However, some algorithms have high latency, and low throughput but suffer from high computational complexity. To overcome these issue a novel efficient Spotted Hyena Optimizer based Multi-User Detection for Polar Encoder (SHO-MUD) has been proposed for enhancing the throughput and reduce the latency. To increase spectrum, throughput, and energy efficiency, the SHO-MUD technique that has been suggested combines a polar encoder (PE) multiplexed with OFDMA with parity check polar coding (PCPC). PCPC-PE uses a system-configurable transmission rate to increase diversity gain and coding process dependability. To achieve optimum resource use over several data blocks, users are scheduled using the Spotted Hyena Optimizer (SHO) approach in conjunction with the MPA. The SHO scheduling efficiently allocates and schedules resources, resulting in a throughput gain of 0.6 bits per second. The suggested system provides user fairness by assuring an equal throughput of 1.55 bits/sec for all users.
