We present a generalized electrostatic SWAP gate realized in a chain of two double quantum dots operated in the single-electron regime. Using a minimalist tight-binding model, we derive analytical results and corroborate them with numerical simulations. We exploit the charge anticorrelation arising from Coulomb repulsion and quantify the resulting entanglement generation. We contrast classical and quantum descriptions and show how device geometry and coupling strengths govern entanglement dynamics and gate performance. The results are relevant to cryogenic, CMOS-compatible quantum technologies and suggest a route toward large-scale semiconductor implementations of quantum logic. Finally, we outline a systematic procedure for translating classical electrostatic logic gates into single-electron quantum gates.
Optical through silicon vias (OTSVs) have been regarded as a promising alternative to conventional (electrical) through silicon vias (TSVs) for the next-generation electro-optic heterogeneous integration. This study systematically examines the influence of fabrication imperfections on the transmission performance in terms of incident light misalignment, via geometry variation, and sidewall roughness. The results demonstrate that over a finite range of beam widths, the insertion loss can be maintained at a relatively low level of less than −0.16 dBm, and this low-loss window broadens with increasing via diameter. Moreover, an increased diameter exhibits greater tolerance to the lateral offset, as for 10 μm, 20 μm, and 30 μm vias, the insertion loss rises to 3 dB at axis misalignments of 5 μm, 10 μm, and 15 μm, respectively. Additionally, smaller-diameter OTSVs are considerably more sensitive to sidewall slope angles than their larger-diameter counterparts. Additionally, minimizing the sidewall roughness is critical for maximizing the coupling efficiency, which suggests that the etch-passivation shift needs to be as quick as possible during the deep reactive ion etch (DRIE) process. With the proposed fabrication approach and comprehensive analysis of fabrication imperfection factors, this study provides essential insights for the development of high-performance OTSVs in advanced 3D optoelectronic integration.
This paper presents a time-domain closed-loop resistive temperature sensor architecture. The design employs a frequency-locked loop (FLL)-based oscillator as the sensing element, generating a monotonic frequency response to temperature variations. The output frequency is digitized on-chip and converted into a temperature code. Within the oscillator core, a switched-capacitor technique converts frequency to voltage for closed-loop control, reducing charging/discharging voltage swings and significantly lowering dynamic power consumption. The FLL topology enhances frequency stability, minimizes distortion, and suppresses power supply sensitivity. Fabricated in a 180 nm CMOS process with a core area of 0.12 mm2, the sensor achieves a peak-to-peak inaccuracy of +1.2 °C/−0.9 °C from −40 °C to 125 °C. Operating at 1 V, the circuit consumes only 10 μW with a resolution of 51 mK within 12 ms.
Processing-in-memory and in-memory computing (PIM/IMC) are increasingly explored to mitigate the von Neumann data-movement bottleneck that limits deep neural network (DNN) performance and energy efficiency. Progress, however, remains fragmented across device substrates, architectural prototypes, mapping and scheduling methods, compiler toolchains, and benchmarking practices, making results hard to compare and slowing deployment. This survey synthesizes developments from 2019–2025 along four coupled axes: (i) memory substrates and architectural design, (ii) mapping, partitioning, and scheduling, including learning- and graph-based strategies, (iii) compilers and end-to-end deployment flows, and (iv) benchmarking datasets, metrics, and reporting norms. Drawing on over twenty representative platforms spanning static random-access memory (SRAM) and dynamic random-access memory (DRAM), emerging non-volatile, capacitive, and photonic substrates, we clarify the trade-offs separating analog/charge-domain IMC from digital SRAM/DRAM-centric PIM, including reported peaks up to 600 TOPS/W and 1.5 TOPS/mm2. We organize mapping frameworks into a unified reference taxonomy, identify recurrent evaluation pitfalls that undermine reproducibility, and highlight persistent gaps in training support, robustness under non-idealities, and coverage of large-scale GNN workloads. Finally, we outline a five-phase roadmap from benchmark standardization to industrial validation toward compiler-integrated, GNN-informed PIM/IMC systems validated on production-scale workloads.
In MOSFETs, mobility enhancement is a key factor for improving the electrical performance and enabling their use in new applications, such as low-power, digital, and medical applications. This mobility improvement can be technically achieved by using different techniques that exploit the complex behavior of mobility (Coulomb, phonon, and surface roughness mobilities). Previous reviews have primarily focused on two main technologies: the introduction of mechanical stress and crystallographic orientation. Therefore, this review summarizes all key techniques that can enhance mobility, and each of these techniques is linked to a physical origin. Mechanical stress notably affects phonon mobility, whereas silicon thickness and channel impurities mainly affect the Coulomb mobility. Moreover, the dielectric oxide type, heat treatments, surface cleaning, ionic implantation in the oxide, and oxynitrides affect surface roughness mobility. In addition, the crystallographic orientation affects Coulomb, phonon, and surface roughness mobilities. Furthermore, the study of the series resistance engineering also affects the performance. Therefore, the simultaneous use of multiple of these techniques leads to an enhancement of the effective mobility at low, medium, and high effective electric fields, and the combined effect results in a more significant mobility increase.
